Method of manufacturing dual gate logic devices

Details Method of manufacturing dual gate logic devices Method of manufacturing dual gate logic devices

2001-06-12

2003-07-22

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S283000, C438S303000, C438S176000, C438S151000, C438S163000

Reexamination Certificate

active

06596597

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to semiconductor devices formed on a bulk single-crystal semiconductor substrate and, more particularly, to dual gate logic semiconductor devices composed of germanium-containing gate conductors and manufactured by a self-aligning process.
BACKGROUND OF THE INVENTION
For complimentary metal on silicon integrated circuits (CMOS ICs) the main performance factors are speed, power dissipation, and device packing density. Therefore, over the past several decades, integrated chip manufacturers have had as one major goal the reduction in microelectronic device size. Both manufacturer and consumer benefit from this reduction in size either by reduced cost or greater performance characteristics. However, the mere reduction in size of the components in the IC will lead to undesirable IC performance problems. In particular, power dissipation due to increased device leakage currents may increase or circuit speed may be degraded. Reliability problems that can afflict metal on silicon field effect transistors (MOSFETs) might also be worsened, including hot-carrier degradation, gate-oxide wearout and electromigration. Clearly, if the degree of process control is not increased, variations in these parameters will become larger (on a percentage basis) as the devices become even smaller. Therefore, it is necessary for the manufacturer of such devices to utilize novel designs and employ processes having tighter processing controls that will mitigate performance and reliability problems, while still providing higher packing densities.
One particular difficulty in the manufacturing processes of some planar double-gate MOSFET devices is that the top and bottom gate conductors may not be self-aligned to each other, and the gate conductors may be of varying widths. Device yield and performance can be significantly constrained by such misalignment of the gate-conductors, and by large deviations in relative channel length. For example, it is reported that misalignment will cause extra gate to source/drain overlap capacitance as well as loss of current drive. Additional information on the effect of misalignment is described by Tanaka of Fujitsu in the 1994 VLSI Symposium.
Another difficulty in the manufacturing processes of these planar double-gate MOSFET devices is that the channel thickness is not of uniform thickness and/or uniform purity. For example, double-gate MOSFET devices should have a uniform and thin (10 to 25 nm) silicon channel. Typically, previous manufacturing processes formed this channel using epitaxially grown silicon via such processes as chemical vapor deposition or sputtering. These processes however, do not necessarily provide sufficient uniformity in thickness or purity, the latter due to entrapment of impurities. As will be described in detail hereinbelow the present invention utilizes a single crystal silicon wafer that is ground and polished to high precision to provide a silicon channel having physical and electrical properties that are superior to the prior art epitaxially grown silicon channels. References to prior art dual-gate MOSFET manufacturing processes can be found in Jong-Ho Lee, et al. IEEE IEDM99-71 through IEDM99-74; Hon-Sum Philip Wong, et al., IEEE IEDM98-407 through IEDM98-410; and Hon-Sum Philip Wong, et al., IEEE IEDM97-427 through IEDM97-429.
Over the years the preeminent semiconductor material for use in integrated chip technology has been silicon. For example, S. Wolf and R. N. Tauber in SILICON PROCESSING (copyright 1986) Volume 1 page 1 state “Germanium was the original semiconductor material used to fabricate diodes and transistors. The narrow bandgap of Ge (0.66 eV), however, causes reverse-biased p-n junctions in Ge to exhibit relatively large leakage currents. This limits the operation to temperatures below about 100° C. In addition, integrated circuit planar processing requires the capability of fabricating a passivation layer on the semiconductor surface. Germanium oxide could act as such a passivation layer but it is difficult to form, is water soluble, and dissociates at 800 C. These limitations make Ge an inferior material for the fabrication of integrated circuits, compared to silicon”.
The use of germanium and germanium alloys has been reported in prior references as gate conducting materials, for example see GERMANIUM ETCHING IN HIGH DENSITY PLASMAS FOR 0.18 MICRON COMPLENTARY METAL-OXIDE-SEMICONDUCTOR GATE PATTERNING APPLICATIONS, C. Monget, A. Schiltz, O. Joubert, L. Vallier, M. Guillermet, B. Tormen, J. Vac. Sci. Technol. B, Vol 16, 1998, p1833-1840. However, none of these references describe, teach, or contemplate the instant inventive feature of selectively etching-back these germanium containing gate conducting materials vis-à-vis the silicon channel.
SUMMARY OF THE INVENTION
The present invention provides for novel manufacturing processes and double- or dual-gate logic devices therefrom that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. These characteristics are important to the industry because device yield and performance can be significantly constrained by such misalignment of the gate conductors, and by large deviations in relative channel length. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. As mentioned supra, changes to the dimensions of the channel can cause adverse performance characteristics.
Also, many prior art planar dual-gate structures rely on the formation of lateral epi-silicon layers for the fabrication of the channel area. Defects in this epi layer can significantly reduce device yield and performance. The present invention alleviates this problem by preferentially utilizing a single-crystal silicon wafer as the channel material.
Therefore, in one aspect of the present invention, a process is described for formation of a uniformly thin channel comprising single-crystal silicon.
In another aspect of the present invention, a process involves etching to generate pillars or stacks of self aligned dual gate MOSFETs via the juxtaposition of overlapping germanium-containing gate conductor regions and vertically etching through regions comprising both gate conducting material and dielectric insulating material. The edge formed by vertically etching through both germanium-containing gate conductor regions provides for essentially a perfect self-aligned dual gate stack.
In yet another aspect of the invention, a process is described wherein the gate conductor material can be selectively etched without etching the channel material.


REFERENCES:
patent: 5414288 (1995-05-01), Fitch et al.
patent: 5612552 (1997-03-01), Owens
patent: 5801089 (1998-09-01), Kenney
patent: 5981345 (1999-11-01), Ryum et al.
patent: 6429484 (2002-08-01), Yu
patent: 2001/0028067 (2001-10-01), Awano
Jong-Ho Lee, et al., IEEE IEDM 99-71 through IEDM99-74.
Hon-Sum Philip Wong, et al., IEEE IEDM 98-407 through IEDM 98-410.
Hon-Sum Philip Wong, et al., IEEE IEDM 97-427 through IEDM 97-429.

Affiliated with

Also associated with

Rating

Method of manufacturing dual gate logic devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing dual gate logic devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing dual gate logic devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3096693