Method of reducing plasma charging damage during dielectric...

Details Method of reducing plasma charging damage during dielectric... Method of reducing plasma charging damage during dielectric...

2001-12-07

2003-09-02

Nguyen, Viet Q. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S687000, C438S700000

Reexamination Certificate

active

06613666

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the alleviation of charge buildup on integrated circuit components during dry plasma etching of semiconductor interconnect feedthrough structures.
2. Brief Description of the Background Art
In the quest for ever-higher circuit densities in modem very large scale integrated circuit semiconductors, engineers have moved from conventional chip layouts, in which interconnects between active regions on the chip are formed by metallic, generally aluminum, conductors in the plane of the devices, connected layer-to-layer mostly at the outer edges, to dual damascene architecture. In a dual-damascene structure, multiple layers of active devices are separated by layers of dielectric material, which are traversed within a given layer by trenches filled with conductive materials, which in turn are connected layer-to-layer by interconnects formed by filling through-openings with conductive materials. These contact openings, typically referred to as vias, are etched through the intervening dielectric layer or layers.
These trenches and contact openings are etched in the dielectric layers by means of dry etching, utilizing a plasma generated by exposing appropriate etchant source gases, often halogen-comprising gases, to powerful electromagnetic fields. The resultant plasma consists of free electrons, positively charged ions, and various high energy species of the plasma source gas. The workpiece to be etched typically has a desired pattern superimposed upon it in some form of mask. The mask is generally formed photolithographically upon an organic photoresist material, which is developed to provide open areas where etching is desired.
To achieve anisotropic etching, that is, etching which is generally unidirectional, so that positively charged active species travel vertically downward through the opening in the resist layer toward the etch front within the deepening etched feature, the workpiece is maintained at a negative electrical potential. This serves to accelerate positively-charged species toward the target surface, but leaves the electrons in the plasma less able to penetrate to the bottom of the etched feature.
This phenomenon, the ability of only positively charged high energy species to penetrate to the lower regions of the etch front, while electrons accumulate near the top of the opening, is called electron shading. The electron shading effect is self-perpetuating, since the accumulation of electrons near the opening creates a local electric field which further repels electrons from entering, but continues to easily permit the positively charged high energy species, such as ions, accelerated by the electrical potential, to penetrate to the full depth of the etched feature. When the resultant positive charge near the bottom of the feature becomes sufficiently high, it results in a tunneling current which can do severe damage to underlying layers.
The aspect ratio of a feature typically refers to the ratio of the depth of the feature to its smallest horizontal cross-sectional dimension. The electron shading effect, and the resultant charging damage to the structure, begin to be significant in etched features having an aspect ratio greater than about 2. The electron shading effect gets worse as the aspect ratio increases, since the electron accumulation near the opening and top sidewalls of the feature makes it increasingly difficult for anything but the positively charged high energy species to get past that entrance and any distance down into the deepening etched feature.
FIGS. 1A-1G
show a typical set of process steps for creating a dual damascene structure. Electron shading effects are often a serious problem during fabrication of dual damascene structures.
In
FIG. 1A
, a conductor
102
, such as copper or aluminum or alloys thereof, is embedded in a dielectric
100
. An upper portion of the conductor is contacted at sidewall
103
by a layer of a first dielectric hardmask
104
. The upper surface
105
of dielectric hardmask layer
104
and the upper surface
107
of conductor
102
, are covered by an etch stop layer
106
, which is typically a dielectric such as Si
3
N
4
, SiON, or SiC. A layer of dielectric
108
, which is typically a low-k dielectric overlies the etch stop layer
106
, and is itself overlain by a second dielectric hardmask layer
110
. (A “low-k dielectric” is one with a relative dielectric permitivity, &kgr;, less than that of SiO
2
, or less than about 3.9.) A via or other contact opening
116
has been etched through dielectric hardmask layer
110
and dielectric layer
108
, to the etch stop layer
106
.
In
FIG. 1B
, a layer of photoresist material
118
has been applied covering the surface of the structure, and partially filling in the contact opening
116
.
In
FIG. 1C
, the photoresist layer
118
has been developed, providing a patterned mask for etching of a trench which will overlie the contact opening
116
.
In
FIG. 1D
, anisotropic etching is being performed to form trench
120
through dielectric hardmask layer
110
and partly into dielectric layer
108
. It is at this point in the prior art etching process to produce trench
120
that the problem of electron shading arises, as illustrated in FIG.
1
D. Accumulations of excess electrons
130
form an unbalanced negative charge near the entrance
126
and on the upper sidewalls
128
of contact opening
116
, and to a lesser extent on the upper sidewalls
124
of developing trench
120
. As positively charged energetic species
132
continue to reach the bottom
117
of contact opening
116
, but few if any electrons
130
are able to do so, a corresponding accumulation of excess positive charge builds up there, causing a tunneling current
134
which can do serious damage to the underlying conductor
102
. Such damage is illustrated by numerals
136
in
FIGS. 1E through 1G
.
In
FIG. 1E
, trench
120
has been etched, directly over contact opening
116
, through dielectric hardmask layer
110
and dielectric layer
108
. At the same time, the bottom
117
of contact opening
116
has been etched down at least partially through etch stop layer
106
.
Subsequently, the residue of photoresist layer
118
has been removed, as illustrated in FIG.
1
F. Finally, in
FIG. 1G
, the remainder of the etch-stop layer
106
at the bottom of contact opening
116
has been removed, to permit electrical contact with the conductor
102
, as illustrated in FIG.
1
G. Contact opening
116
and trench
120
are subsequently filled with conductive material to form the interconnect between the lower and upper layers of devices. This process can be repeated as desired to form a multilayered structure in which the active layers are electrically interconnected by conductive fill material placed in the contact openings and trenches.
Various techniques have been used in an attempt to reduce or eliminate charging damage to semiconductor devices occurring during the etching process. For example, U.S. Pat. No. 5,468,341, to Samukawa (See Abstract.), discloses a method and apparatus wherein pulse modulation of the electric fields producing the etching plasma are controlled to produce a pulse interval shorter than about 10 &mgr;sec. This is said to provide advantageous process conditions, including a reduction in charge accumulation. U.S. Pat. No. 5,441,849, to Shiraishi, et al (See abstract.) discloses a method of solving a distinct but similar problem of electrical charge accumulation During the formation of the latent image in a photoresist layer, the photoresist is exposed to a charged particle beam, where electrical charge accumulation causes positional deviation of the imaged pattern. By using a bottom-resist layer of material which can be rendered conductive by simultaneous exposure to actinic radiation (such as ultraviolet light, X-ray, or infrared light), the charge accumulation is alleviated.
SUMMARY OF THE INVENTION
The present invention reduces the amount of charging damage caused by electron shading during the process o

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