Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
1999-12-23
2003-03-18
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S711000
Reexamination Certificate
active
06536002
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices and more particularly to redundancy circuits for integrated circuit memory devices.
BACKGROUND OF THE INVENTION
One of the major determinants of the cost of producing memory chips is wafer yield, which may be defined as the ratio of non-defective chips to total chips fabricated on a given wafer. In general, the higher the integration density of the memory chip, the higher the probability that one or more memory cells thereof will be defective. Thus, the higher the integration density of the chips fabricated on a given wafer, the lower the wafer yield as a result of defective memory cells. Accordingly, the need for devices which correct defects in order to enhance wafer yield may be more acute with the advent of high-density memory chips. One way to correct memory cell defects in order to enhance wafer yield is the provision of a redundant memory circuit which includes one or more redundant rows and/or columns of memory cells that may be used to replace rows and/or columns of the main memory array which are found to be defective, for example, during testing, wafer sort, or other processes. In general, the redundant rows and/or columns have unspecified addresses and redundant decoders coupled thereto. The redundant decoders can be programmed to match the addresses of rows and/or columns which are determined to be defective. The defective rows and/or columns may further be decoupled or disabled.
In operation, when a memory read or write cycle is executed, the redundant decoders are responsive to the addresses of the disabled defective rows and/or columns, thereby effectively replacing the defective rows and/or columns with the redundant rows and/or columns. This technique of replacing defective rows and/or columns with redundant rows and/or columns is oftentimes referred to as repairing defective memory cells.
A typical programmable redundant decoder includes polysilicon fusible links, i.e., fuses, connected to respective address bit lines of a row address or column address buffer, depending upon whether the redundant decoder is a redundant row or column decoder, respectively. In order to program such a redundant decoder with the address of a column or row of memory cells having a defective memory cell, selected ones of the fuses are cut/blown, e.g., by means of a laser.
One approach to replacing a defective column and/or row address with a redundant column and/or row address is described in U.S. Pat. No. 5,325,334 (“the '334 patent”) which is incorporated herein by reference. As described in the '334, patent a plurality of fuses within a fuse box array are programmed so as to be selectively cut or burnt to select a redundant memory cell (column) responsive to an address of a defective cell (column). When a column address signal corresponding to a defective column is input to the fuse box array, a redundant column is activated. The activated redundant column replaces the defective column. A plurality of fuse boxes are arranged in the fuse box array to allow repair of a plurality of defective columns. Each of the fuse boxes shares a column address signal input, and includes a plurality of fuses for use in programming a column address corresponding to a defective column. When a defective column address is input to a fuse box, a redundant column driver gate is driven in response to a first output signal provided by a block selection control circuit to select a predetermined redundant column.
However, in the circuit discussed in the '334 patent, use or non-use of a plurality of fuse boxes arranged to repair defective columns is determined by the number of generated defective columns. Therefore, different loads can be applied respectively to lines of a column address signal bus depending on whether the fuses are open or closed. The difference in load between the column address signal lines may cause skew between column address signals. Such skew may lower the transmission speed of the column address signals.
Additional redundancy systems are described, for example, in U.S. Pat. No. 5,742,547 to Lee, entitled “Circuits for Block Redundancy Repair of integrated Circuit Memory Devices; ” U.S. Pat. No. 5,761,138 to Lee et al., entitled “Memory Devices Having A Flexible Redundant Block Architecture” and U.S. Pat. No. 5,777,931 to Kwon et al., entitled “Synchronized Redundancy Decoding Systems and Methods for Integrated Circuit Memory Devices, ” (which provides redundancy circuits without transfer gates) the disclosures of all of which are hereby incorporated herein by reference.
SUMMARY OF THE INVENTION
The present invention provides integrated circuit memory device redundancy circuits that include a plurality of transistors and fuses, a respective transistor and a respective fuse being serially coupled between a respective address line input and a logic circuit to generate a selection signal for a redundant memory cell in response to a predetermined address on the address line inputs. A buffer circuit is coupled between the address line inputs and an address bus of the integrated circuit memory device. In one embodiment, a decoder is coupled between the address bus of the integrated circuit memory device and a plurality of external address inputs of the integrated circuit memory device. A redundancy enable control circuit may be provided that includes a main fuse and that generates a fuse enable signal in response to opening of the main fuse wherein the plurality of transistors are responsive to the fuse enable signal. The fuse enable signal may be generated in response to a power up signal. More particularly, the fuse enable signal may be generated for an initial period responsive to the power up signal when the main fuse is open and when the main fuse is closed and generated for a second period following the initial period only when the main fuse is open.
In one embodiment, the transistors are MOS transistors and the gates of the MOS transistors are coupled to the fuse enable signal. More particularly, the MOS transistors may be NMOS transistors each having a source coupled to one of the address line inputs and a drain coupled to one of the fuses. The redundancy circuit may also include a plurality of PMOS transistors each having a gate coupled to the fuse enable signal, a source coupled to a first reference voltage and a drain coupled to one of the fuses. The redundancy enable control circuit in one embodiment includes a PMOS transistor having a gate coupled to the power up signal and a source connected to a first reference voltage and an NMOS transistor having a gate coupled to the power up signal and a source connected to a second reference voltage. The main fuse may be coupled between the drains of the PMOS transistor and the NMOS transistor. The redundancy enable control circuit may also include a latch that latches the fuse enable signal.
In another embodiment of the present invention, the redundancy circuit includes a main memory block having a plurality of cells. The main fuse is associated with one of the plurality of cells. The main memory block is coupled to and addressed by the address bus of the integrated circuit memory device. The redundancy circuit further includes a redundancy memory cell block including the redundant memory cell. The redundant memory cell is selected responsive to the selection signal. The redundancy memory cell block preferably includes a plurality of redundant memory cells each having an associated plurality of transistors and fuses, a respective transistor and a respective fuse being serially coupled between a respective address line input and a logic circuit to generate a selection signal for the associated one of the redundant memory cells in response to a predetermined address on the address line inputs. An associated buffer circuit may be coupled between the corresponding address line inputs and the address bus of the integrated circuit memory device. An associated redundancy enable control circuit may include a main fuse and generate a fuse enable
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Ton David
LandOfFree
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