Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-08
2003-04-22
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
06553525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to testing integrated circuits and in particular to a method and apparatus for selectively testing arrays in an integrated circuit. Still more particularly, the present invention relates to a method and apparatus for selectively testing a given array.
2. Description of Related Art
In general, integrated circuit arrays are tested by providing a known data input at a known address to the array and comparing the output to the expected output. One well known and widely used prior art system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself. This circuit also is called an array built in-self test (ABIST) circuit or engine. This type of technology allows for high speed testing without having to force correspondence between the array and input/output connections to the chip itself. Random access memory on a chip, such as the memory provided for processors, are usually tested using an ABIST engine. It is increasingly common to have multiple arrays present on a chip. In testing these arrays, some arrays only need a subset of some tests that are performed on the set of arrays. Further, some tests will not work on all of the arrays. As a result, present testing mechanisms for arrays using ABIST engines may require a mechanism to disable the participation of some arrays from ABIST engines while testing others.
Also, it may be desirable to exploit the fact that ABIST engines can be used to write all the addresses in arrays, to initialize them at power on time (Power on reset). The initialization sequence requirements for various arrays may be incompatible, thereby requiring that their ABISTs be run at separate times without contaminating the contents of the arrays that were initialized by the earlier ABIST executions.
Generation and simulation of test patterns for the combinatorial logic in a digital logic chip which uses scan design is much more efficient if the effects of sequential logic (like embedded RAMs) do not have to be taken into account, therefore, it may be desirable to force known values on the outputs of one or more arrays that is independent of their contents. This behavior can also be desirable during the design debug and analysis phase for early versions of a design.
In the above mentioned environments it would be advantageous to have an improved method and apparatus for selectively enabling and disabling arrays for testing and/or design debug.
SUMMARY OF THE INVENTION
The prevent invention provides a method and apparatus for selectively enabling or disabling a plurality arrays on a processor with an on chip built in self test engine on the processor. A subset of the plurality arrays on the processor is selected for testing using a control mechanism to selectively enable testing of the subset. Data patterns from the on chip built in self test engine are sent to the plurality arrays on the processor. A response is received at the on chip built in self test engine from the plurality arrays. The response from the plurality arrays is compared to an expected response using the on chip built in self test engine.
REFERENCES:
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patent: 5416740 (1995-05-01), Fujita et al.
patent: 5633877 (1997-05-01), Shephard, III et al.
patent: 5796745 (1998-08-01), Adams et al.
patent: 6061813 (2000-05-01), Goishi
International Business Machines - Corporation
Nichols Michael R.
Salys Casimer K.
Tu Christine T.
Yee Duke W.
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