Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-22
2003-01-14
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S289000, C257S282000
Reexamination Certificate
active
06506640
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices. The invention has particular applicability in manufacturing high-density metal oxide semiconductor field effect transistors (MOSFETs) with submicron design features.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor devices require design features of 0.18 &mgr;m and below, such as 0.15 &mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitation of conventional semiconductor manufacturing techniques.
The principle elements of a typical MOSFET device generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped conductor and a gate input signal is applied to the gate electrode via a gate terminal. Heavily doped source and drain regions are formed in the semiconductor substrate and are connected to source and drain terminals. A channel region is formed in the semiconductor substrate below the gate electrode and separates the source and drain regions. The gate electrode is separated from the semiconductor substrate by a gate oxide layer to prevent current from flowing between the gate and the source and drain regions or the channel region.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electrical field is set up in the channel region. By varying the transverse electric field between the source and drain regions, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner, an electric field controls the current flow through the channel region. The channel is typically lightly doped with an impurity type opposite to that of the source/drain regions, and the impurity concentration profile is typically uniform from the surface toward the direction of depth, as shown byline
10
in FIG.
1
.
Such an MOS structure is however susceptible to a “latch up” phenomenon which establishes very low resistance path between V
DD
and V
SS
power lines, allowing excessive current to flow across power supply terminals. The susceptibility to “latch up” arises from the presence of complementary parasitic bipolar transistor structures, which result from the fabrication of complementary MOS (CMOS) devices. Since they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like a pnpn diode. In the absence of triggering currents, such diodes act as reverse-biased junctions and do not conduct. However, it is possible for triggering currents to be established in a variety of ways during abnormal circuit operation conditions. Since there are many such parasitic pnpn structures on a single chip, it is possible to trigger any one of them into “latch up” and cause the device to cease functioning or even destroy the device itself due to heat damage caused by high power dissipation.
Many approaches have been introduced, such as a retrograde well structure, to control or even eliminate “latch up”. As shown by curve
12
in
FIG. 1
, the retrograde well structure normally has an impurity concentration peak located deep under the surface of a silicon substrate. Such a retrograde well structure has been preferably formed by ion implanting impurity atoms (i.e., boron for an NMOS device) under predetermined conditions, for example, implantation concentration, energy, and duration, so as to form a predetermined impurity concentration peak value at a predetermined depth 1 below the top surface of the substrate. However, formation of a P type retrograde channel by ion implanting boron is problematic, principally due to the ease with which boron atoms diffuse in silicon substrates. The rapidity of boron atom diffusion upon thermal treatment for post-implantation activation/lattice damage relaxation disadvantageously results in a relatively flat concentration profile, as shown by curve
14
in FIG.
1
.
Thus, a need exists for improved semiconductor manufacturing methodology for fabricating MOSFET devices which do not suffer from the above-described drawback associated with the rapid diffusion of boron atoms in silicon substrates. Moreover, there exists a need for an improved process for fabricating MOS transistors with reduced short-channel effects, such as, “punch-through”, which process is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a simplified, efficient, and production worthy method for manufacturing a semiconductor device which is less susceptible to “latch-up” and “punch-through” effects.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: ion implanting, a first impurity of a first conductive type into a semiconductor substrate to form a sharp retrograde impurity region having a first impurity concentration peak formed at a first depth below the top surface of the semiconductor substrate; and ion implanting a second impurity of the first conductive type into the semiconductor substrate to form a shallow impurity region having a second impurity concentration peak at a second depth below the top surface, the second depth less than the first depth.
Another aspect of the present invention is a semiconductor device comprising: a semiconductor substrate having a top surface; a retrograde impurity region containing a first impurity of a first conductive type, having a first impurity concentration peak at a first depth below the top surface; and a shallow impurity region containing a second impurity of the first conductive type, having a second impurity concentration peak at a second depth below the top surface, the second depth less than the first depth.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustrating the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.
REFERENCES:
patent: 6245618 (2001-06-01), An et al.
patent: 6245649 (2001-06-01), Buller et al.
patent: 6312981 (2001-11-01), Akamatsu et al.
Hao Ming Yin
Ishida Emi
Nayak Deepak K.
Cao Phat X.
Trinh Hoa B.
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