Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-20
2003-03-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S621000, C438S631000, C438S958000
Reexamination Certificate
active
06531389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming vias through dielectric layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming with attenuated contact resistance incompletely landed vias through dielectric layers to access patterned conductor layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become more common in the art of microelectronic fabrication to form interposed between the patterns of narrow linewidth patterned microelectronic conductor layers within microelectronic fabrications low dielectric constant microelectronic dielectric materials. Within the context of the present invention, narrow linewidth patterned microelectronic conductor layers within microelectronic fabrications are typically characterized by a linewidth of less than about 0.5 microns, more typically of a linewidth of from about 0.1 to about 0.4 microns. Similarly, low dielectric constant microelectronic dielectric materials when employed within microelectronic fabrications formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications are typically characterized by a dielectric constant of less than about 4.0, more typically of a dielectric constant of from about 1.5 to about 3.8. In comparison, conventional silicon containing dielectric materials, such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials, typically have a dielectric constant in a range of from about 4 to about 8 .
Within the context of the present disclosure, low dielectric constant microelectronic dielectric materials may include, but are not limited to: (1) spin-on-glass (SOG) low dielectric constant dielectric materials (such as but not limited to silicate spin-on-glass (SOG) dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials)); (2) spin-on-polymer (SOP) low dielectric constant dielectric materials (such as but not limited to polyimide spin-on-polymer (SOP) dielectric materials, poly arylene ether spin-on-polymer (SOP) dielectric materials and fluorinated analogs thereof; (3) amorphous carbon dielectric materials (including fluorinated analogs thereof); and (4) fluorinated conventional silicon containing dielectric materials (such as but not limited to fluorosilicate glass (FSG) dielectric materials).
Low dielectric constant dielectric materials are desirable when formed interposed between the patterns of narrow linewidth patterned microelectronic conductor layers within microelectronic fabrications since such low dielectric constant dielectric materials provide microelectronic fabrications with enhanced microelectronic fabrication speed, reduced patterned microelectronic conductor layer parasitic capacitance and reduced patterned microelectronic conductor layer cross-talk.
While microelectronic fabrications having formed therein narrow linewidth patterned microelectronic conductor layers having formed interposed between their patterns low dielectric constant microelectronic dielectric materials are thus desirable within the art of microelectronic fabrication, microelectronic fabrications having formed therein narrow linewidth patterned microelectronic conductor layers having formed interposed between their patterns low dielectric constant microelectronic dielectric materials are nonetheless not formed entirely without problems in the art of microelectronic fabrication.
In particular, it is known in the art of microelectronic fabrication that when forming a conductor stud layer into a via formed through a dielectric layer formed of a low dielectric constant microelectronic dielectric material to access a narrow linewidth patterned microelectronic conductor layer within a microelectronic fabrication there is often experienced contact resistance increases since many low dielectric constant microelectronic dielectric materials readily sorb and desorb moisture and solvents which may contribute to oxidation or corrosion of the conductor stud layer and/or the narrow linewidth patterned microelectronic conductor layer. Similarly, such sorbtion and desorbtion induced contact resistance increases are often exacerbated under circumstances where the via formed through the microelectronic dielectric layer to access the narrow linewidth patterned microelectronic conductor layer is not completely landed, but rather partially offset, from the narrow linewidth patterned microelectronic conductor layer, since under such circumstances there is typically not formed a contiguous and reliable interface between the narrow linewidth patterned microelectronic conductor layer and the conductor stud layer.
It is thus towards the goal of forming within the art of microelectronic fabrication, with attenuated contact resistance, conductor stud layers into vias through dielectric layers to access patterned conductor stud layers within the microelectronic fabrications, where the vias are incompletely landed upon patterned conductor layers within those microelectronic fabrications, that the present invention is directed. More particularly, the present invention is directed towards the foregoing object under circumstances where the dielectric layers are formed of low dielectric constant dielectric materials.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic conductor structures and/or microelectronic dielectric structures with desirable properties within microelectronic fabrications.
For example, Wu et al., in U.S. Pat. No. 5,432,073, discloses a method for forming within a microelectronic fabrication a conductor stud layer into a via formed through a dielectric layer formed at least in part of a spin-on-glass (SOG) dielectric material to access a patterned conductor layer within the microelectronic fabrication, while avoiding a contact resistance increase of the conductor stud layer with respect to the patterned conductor layer. The method realizes the foregoing object by degassing the spin-on-glass (SOG) dielectric material exposed within the via at a temperature of from about 300 to about 500 degrees centigrade prior to forming within the via the conductor stud layer.
In addition, Kishimoto et al., in U.S. Pat. No. 5,506,177, discloses a method for forming within a microelectronic fabrication a spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction with enhanced crack resistance and enhanced moisture resistance, while employing a hydrogen silsesquioxane (HSQ) spin-on-glass (SOG) low dielectric constant dielectric material when forming a spin-on-glass (SOG) planarizing layer within the spin-on-glass (SOG) sandwich composite planarizing dielectric layer construction. The method realizes the foregoing object by employing a two step thermal annealing method for curing and thermal annealing of the spin-on-glass (SOG) planarizing layer, wherein a second thermal annealing step within the two step thermal annealing method reflows a thermally cured hydrogen silsesquioxane spin-on-glass (SOG) dielectric material formed within a first thermal annealing step within the two step thermal annealing method.
Further, Havemann, in U.S. Pat. No. 5,565,384, discloses a method for forming, with enhanced microelectronic fabrication stability, reliability and performance, a via throug
Shue Shau-Lin
Wang Mei-Yun
Ackerman Stephen B.
Rocchegiani Renzo N.
Saile George O.
Smith Matthew
Stanton Stephen G.
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