Semiconductor memory device for reducing damage to...

Details Semiconductor memory device for reducing damage to... Semiconductor memory device for reducing damage to...

2001-09-05

2003-03-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S298000

Reexamination Certificate

active

06537875

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and fabrication method thereof, and more particularly, to a semiconductor memory device in which a platinum group metal layer is adopted as a lower electrode, and fabrication method thereof.
2. Description of the Related Art
In order to improve the capacitance of a capacitor of a semiconductor memory device, it is very advantageous to form a lower electrode having a three-dimensional structure that increases the effective surface area of the capacitor while better utilizing available space. However, as the design rule of a semiconductor memory device decreases to below 0.2 &mgr;m, there are many problems with formation of a lower electrode having a three-dimensional structure.
FIGS. 1-4
are cross-sectional views for explaining a method of manufacturing a semiconductor memory device including a conventional capacitor. Referring to
FIG. 1
, after forming an interlevel dielectric layer
13
on a semiconductor substrate
11
such as a silicon substrate, a titanium nitride (TiN) plug
15
is formed within the interlevel dielectric layer
13
. The interlevel dielectric layer
13
may be formed of silicon oxide. Then, a silicon nitride (SiN) layer
17
is formed on the interlevel dielectric layer
13
and the titanium nitride plug
15
, on top of which a mold layer
19
of silicon oxide is formed. Referring to
FIG. 2
, the mold layer
19
and the silicon nitride layer
17
are patterned to form a groove
20
that exposes the titanium nitride plug
15
. As a result, the mold layer
19
and the silicon nitride layer
17
become a mold pattern
19
a
and a silicon nitride pattern
17
a,
respectively. Then, a conductive layer
21
for a lower electrode is provided over the entire surface of the semiconductor substrate
11
on which the groove
20
has been formed. The conductive layer
21
is a platinum group noble metal layer such as a platinum (Pt) layer, a ruthenium (Ru) layer, or an Iridium (Ir) layer. Then, a sacrificial layer
23
for filling the groove
20
is formed over the entire surface of the semiconductor substrate
11
on which the conductive layer
21
has been formed. The sacrificial layer
23
is formed of photo resist or silicon oxide.
Referring to
FIG. 3
, using the mold pattern
19
a
as an etching stopper, the sacrificial layer
23
and the conductive layer
21
are sequentially etched to form a sacrificial pattern
23
a
and a lower electrode
21
a.
Referring to
FIG. 4
, the lower electrode
21
a
is formed by removing the sacrificial pattern
23
a
and the mold pattern
19
a
by wet etching. Then, a capacitor dielectric layer (not shown) and an upper electrode (not shown) are provided over the lower electrode
21
a
to complete a capacitor of a semiconductor memory device.
According to a conventional method of manufacturing a semiconductor memory device, since the conductive layer
21
, such as a ruthenium layer, exhibits low adhesive strength to the mold pattern
19
a
and silicon nitride pattern
17
a,
problems associated therewith occur, for example, the lower electrode
21
a
may collapse. As a result, the lower electrode
21
a
is not formed stably.
Furthermore, according to the conventional method, when removing the mold pattern
19
a,
the adhesive strength between the lower electrode
21
a
and the silicon nitride pattern
17
a
is so low that an oxide layer etching solution may penetrate the interface (in a direction of an arrow of
FIG. 3
) to damage the interlevel dielectric layer
13
.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a semiconductor memory device for stably forming a lower electrode of a capacitor while reducing damage to an interlevel dielectric layer.
It is another objective of the invention to provide a method of manufacturing a semiconductor memory device.
Accordingly, to achieve the above objectives, a semiconductor memory device according to the invention includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole therein to expose a semiconductor substrate. A plug is disposed within the contact hole. The plug may project higher than the top surface of the adhesive pattern. The adhesive pattern prevents a lower electrode of a capacitor from collapsing by sufficiently adhering the lower electrode to the interlevel dielectric pattern. Also, the adhesive pattern prevents damage to the interlevel dielectric pattern during the formation of the capacitor due to high adhesive strength to the plug.
The lower electrode of a capacitor is formed on the plug. The lower electrode of a capacitor has bottom and side wall surfaces, wherein at least a portion of the bottom surface thereof contacts a portion of the plug.
A leakage current preventive pattern is formed on the adhesive pattern and adjacent a portion of the side wall surfaces of the lower electrode. The leakage current preventive pattern prevents an increase in leakage current by preventing a capacitor dielectric layer to be formed on the lower electrode from directly contacting a plug, even if misalignment occurs during the formation of a lower electrode.
The present invention also provides a method of manufacturing a semiconductor memory device. According to the manufacturing method, a contact hole exposing a semiconductor substrate is formed in an adhesive pattern and in an interlevel dielectric pattern on the semiconductor substrate. The adhesive pattern prevents a lower electrode of a capacitor from collapsing by sufficiently adhering the lower electrode to the interlevel dielectric pattern. Also, the adhesive pattern prevents damage to the interlevel dielectric pattern during the formation of a capacitor due to high adhesive strength to a plug to be later formed.
Subsequently, a plug for filling the contact hole or a plug projecting higher than the surface of the adhesive pattern is formed. A groove exposing the plug is formed within a mold pattern. In addition, a leakage current preventive pattern forms on the adhesive pattern. The leakage current preventive pattern prevents the occurrences of the leakage current even if a misalignment of the lower electrode of a capacitor occurs.
Then, the lower electrode of a capacitor contacting the top surface of the plug exposed by the groove is formed.
Then, the mold pattern is removed, thereby completing a semiconductor memory device. As described above, the semiconductor memory device according to the present invention prevents the capacitor lower electrode from collapsing. This is because of the direct contact between capacitor lower electrode and the adhesive pattern having high adhesive strength. The semiconductor memory device can prevent damage to the interlayer dielectric pattern during the formation of the capacitor due to high adhesive strength between the adhesive pattern and the plug. Furthermore, the semiconductor memory device prevents leakage current from increasing by forming the leakage current preventive pattern, preventing a capacitor dielectric layer formed on the lower electrode from directly contacting the plug.


REFERENCES:
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5518948 (1996-05-01), Walker
patent: 6114201 (2000-09-01), Wu
patent: 6274899 (2001-08-01), Melnick et al.
patent: 6326316 (2001-12-01), Kiyotoshi et al.

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