Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-12
2003-04-29
Nelms, David (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000
Reexamination Certificate
active
06555425
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90113552, filed on Jun. 5, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a transistor. More particularly, the present invention relates to a method for manufacturing an MOS transistor with a T-type gate structure.
2. Description of Related Art
With the decrease of size of ICs and the increase of integration of ICs, the wire width, the contact area and junction depth of a device becomes small. In order to efficiently improve the potential of the device and decrease the resistance and RC time delay, a silicide is formed on the surface of the device (such as the surface of the gate and the source/drain) to efficiently decrease the contact resistance.
Typically, the method for manufacturing a silicide on a junction of a device comprises steps of sputtering a metal layer over the transistor after the gate, the spacer of the gate and the source/drain of the transistor are formed. Thereafter, a rapid thermal process is performed to form a silicide on the surface of the gate and the source/drain.
However, the typical method for forming the silicide to decrease the contact resistance consumes many silicon atoms, especially during the formation of a silicon copper film. It is well known that every 100-angstrom-thickness copper should react with a 360-angstrom-thickness silicon to form a silicon copper layer. Therefore, this kind of consumption of silicon leads to the increase of the resistance of the source/drain and the decrease of the operating speed of the device. Moreover, the size of the silicide on the gate is limited by the width of the gate, so that the contribution of the silicide on the gate to the decrease of the resistance of the gate is limited. Additionally, with the decrease of the size of the device, it is easy to induce the bridging effect between the gate and the source/drain by using the typical silicide method. Furthermore, the spacer formed by the conventional method cannot sufficiently avoid the diffusion of the hydrogen ions into the channel during the manufacturing process. Hence, it is easy to induce the boron penetration phenomena so that the threshold voltage of the device will become unstable.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.
In the present invention, since the epitaxial layer formed on the polysilicon layer is relatively large, the resistance of the T-type is decreased and the operating rate of the device can be greatly improved. Moreover, by using the selective epitaxial growth process, the epitaxial layers are respectively formed on the polysilicon layer and the source/drain to decrease the contact resistance. Hence, the problem of the high resistance of the gate and the source/drain caused by over consumption of the silicon atoms in the substrate during the formation of the silicide in the conventional process can be overcome. Furthermore, because the formation of the epitaxial layer does not consume the silicon atoms in the substrate, the problem of the junction leakage induced by shrinking the size of the device can be overcome. Because the spacer is relatively thick and uniform, the diffusion of the hydrogen ions into the channel and the penetration of the boron ions cab be avoided. Therefore, the stability of the threshold voltage of the device can be greatly improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6057185 (2000-05-01), Suenaga
patent: 6194258 (2001-02-01), Wuu
patent: 6255152 (2001-07-01), Chen
patent: 6297107 (2001-10-01), Paton et al.
patent: 6319784 (2001-11-01), Yue et al.
patent: 6359291 (2002-03-01), Liu et al.
Cheng Ellen
Huang Kuo-Tai
Dang Phuc T.
United Microelectronics Corp.
Wu Charles C. H.
Wu & Cheung, LLP
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