Method of fabricating silicon nitride read only memory

Details Method of fabricating silicon nitride read only memory Method of fabricating silicon nitride read only memory

2001-08-10

2002-10-22

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S291000, C438S293000

Reexamination Certificate

active

06468864

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Serial No. 90115049, filed Jun. 21, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a pocket doping region, and more particularly, a method of fabricating a pocket doping silicon nitride read only memory by employing a thermal diffusion method.
2. Description of the Related Art
The gate portion of a conventional erasable programmable read-only memory (EPROM), flash EPROM, or flash electrically erasable programmable read-only memory (Flash EEPROM) comprises a floating gate and a control gate. During data write-in, thermal electrons enter the floating gate via the pocket doping region of the substrate at the lower section of the floating gate, tunneling through the thin silicon dioxide layer located at the lower section of the floating gate, and are trapped in the floating gate so as to store the write-in data.
Conventional floating gates are formed from polysilicon, and as a result of a demand for higher integration in semiconductors, the problem of current leakage occurs. Thus, a conventional solution to this problem is to replace the floating gate with a trapping layer structure formed from silicon oxide-silicon nitride-silicon oxide and to store carriers in the insulating silicon nitride by hot carrier implantation so as to attain the objective of data storage. A silicon oxide-silicon nitride-silicon oxide memory element of the trapping layer is known as a silicon nitride read only memory (NROM), ONO EEPROM or SONOS element based on the method of operation thereof.
A conventional silicon nitride read only memory element includes a substrate having a silicon oxide-silicon nitride-silicon oxide structure (ONO): lower silicon oxide layer, silicon nitride layer, and top silicon oxide dielectric layer. A gate conductive layer is formed on top of the silicon oxide/silicon nitride/silicon oxide structure. A source/drain region is provided in the substrate at the two lateral sides of the silicon oxide-silicon nitride-silicon oxide. A channel region is provided at the lower section of the two lateral sides of the silicon oxide-silicon nitride-silicon oxide structure and between the source/drain region. Furthermore, a pocket doping region is provided at the lower section of the two lateral sides of the silicon oxide/silicon nitride/silicon oxide structure and adjacent to the source/drain region.
Tilt angle ion implantation is used in the convention method of fabricating pocket doping region, and a dopant is implanted into a channel region periphery and the connection of a pre-fabricated source/drain extension. That is, tilt angle ion implantation is used to implant the dopant in the predetermined region. After that, a thermal process is performed so that the implanted dopant is evenly distributed to form a pocket doping region.
Because the pocket doping region employs tilt angle ion implantation to implant a dopant, in the course of implantation, the shape of the region of the implanted dopant cannot be effectively controlled. After the thermal process, the pocket doping region extends into a larger region, causing a length shortening of the channel region positioned below the silicon oxide-silicon nitride-silicon oxide structure.
In the course of the development of higher integration in semiconductor devices, and due to the fact that the pocket doping region formed by the conventional tilt angle implantation process cannot be reduced, in the course of reduction of the gate line width, the channel region positioned below the gate suffers significant shortening, and the pocket doping region adjacent to the source and drain cause an increase of threshold voltage. In other words, the reverse short channel effect affects the electrical property and performance of the device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating a silicon nitride read only memory in which the pocket doping region is formed along the edge of the source/drain and does not cause a channel region shortening so that the element has excellent electrical properties.
In order to solve the above-mentioned drawbacks, the pocket implanted dopant is vertically implanted into a predetermined source/drain region, and at the same time, a thermal process is employed to form buried a source/drain region, so that the pocket implanted dopant thermally diffuses to the channel of the substrate at the bottom of the silicon oxide-silicon nitride-silicon oxide to form the pocket doping region. By means of the rate of the thermal diffusion of the present invention in controlling the size and the configuration of the pocket doping region, the reverse short channel effect can be avoided, breakdown and damage of the element are prevented, and the production yield is improved.
The present invention relates to a method of fabricating silicon nitride read only memory. A trapping layer is formed on a substrate. Next, on the substrate, a patterned photoresist layer is formed, the substrate region at the lower section of the trapping layer masked by the photoresist layer is defined as a channel region, and the substrate region at the lower section of the trapping layer unmasked by the photoresist layer is defined as a source/drain region. A pocket ion implantation step is then performed while using the photoresist layer as a screen. A first dopant is implanted into the source/drain region of the substrate and then the photoresist layer is used as the screen while the source/drain ion implantation step is performed and a second dopant is implanted into the source/drain region of the substrate. After that, the photoresist layer is removed. Next, the trapping layer is used as a screen, and a thermal process is performed so that the substrate surface of the source/drain region is formed into a buried source/drain oxide layer. At the same time, the second dopant at the lower section of the buried source/drain oxide layer is formed into a buried source/drain. The first dopant is formed into the pocket doping region at the edge of the channel region of the buried source/drain periphery as a result of thermal diffusion. Finally, a conductive gate is formed on the substrate.
In accordance with the present invention, a dopant of the pocket doping region is first implanted into the source/drain and the thermal diffusion method is employed to form the pocket doping region. The present method can effectively control the shape of the pocket doping region and avoid the irregular shape formed by tilt angle ion implantation. Moreover, the width of the pocket doping region can be effectively controlled. Thus, the effect of shortening of the channel region can be avoided so as to increase the breakdown voltage of the element.


REFERENCES:
patent: 5837587 (1998-11-01), Wei
patent: 6232166 (2001-05-01), Ju et al.
Wolf, “Silicon Processing for the VLSI Era”, vol. 1, 1986, pp. 303-308.

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