Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-24
2002-11-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S248000, C438S246000, C438S244000, C438S387000, C438S389000, C438S391000, C438S392000
Reexamination Certificate
active
06486024
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to an integrated circuit (“IC”) and method of forming thereof, and more particularly to an integrated circuit vertical trench device and method of forming thereof.
BACKGROUND
The semiconductor industry is continuously trying to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. For example, it is not uncommon for there to be millions of semiconductor devices on a single semiconductor product.
Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device, and devices have approached sizes down to tenths of microns and less. There is some limit, however, as to how far a horizontally oriented semiconductor device can be shrunk, and as devices are made even smaller, it is generally becoming increasingly difficult to further miniaturize a device's horizontal dimensions. In addition, the decreasing horizontal dimensions of semiconductor devices generally tend to create problems in the operational characteristics of the semiconductor devices.
One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor memory is a dynamic random access memory (“DRAM”). A DRAM may include millions or billions of individual DRAM cells, each cell storing one bit of data. A DRAM memory cell typically includes an access field-effect transistor (“FET”) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Semiconductor memory density is typically limited by a minimum lithographic feature size that is imposed by lithographic processes used during fabrication. There is a continuing need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs.
One way of increasing the data storage capacity of semiconductor memories is to reduce the amount of integrated circuit horizontal planar area consumed by each memory cell. For horizontally oriented devices, this may be done by decreasing the size of the access FET or the storage capacitor, or both. This approach has limits, however, due to minimum producible structure size in a given fabrication technology, and the problems associated with devices with small dimensions, such as hot carriers, punch through, and excess leakage.
Another way of providing planar area reduction is the use of a three-dimensional arrangement of the access FET and the storage capacitor. One such arrangement is a planar FET next to a deep trench capacitor. A trench typically has a depth of 5-8 um and an oval top-down-view shape. The trench capacitor has plates which are located vertically along the walls of the trench instead of being parallel to the surface of the integrated circuit substrate. This permits a large capacitance per planar unit area of substrate, while at the same time allowing the device to be of a manageable size for purposes of operation. Alternatively, a vertical transistor with a vertically oriented gate may be fabricated in the trench.
In the prior art, a collar oxide is typically formed on an upper portion of the trench sidewalls, for example, down to about 1.5 microns into the trench. The collar oxide generally provides isolation for the trench devices and prevents the formation of parasitic elements, such as a vertical parasitic transistor in the upper region of the trench. The collar oxide is typically a layer of silicon dioxide with a thickness of about 200-500 angstroms.
There are generally several problems, however, with prior art approaches to fabricating the collar oxide in a vertical DRAM cell. For example, a collar oxide may be formed using a Local Oxidation of Silicon (“LOCOS”) process. With the LOCOS process, a masking step is used to define the length (that is, depth into the trench) of the LOCOS collar. The mask, which may be silicon nitride, is a trench fill layer that has been etched back, or recessed, to the appropriate depth in the trench. A thermal oxide is then grown on the trench sidewalls above the mask. One problem with this approach is that silicon from the trench sidewalls is consumed during the oxidation process, in general requiring a tighter or smaller mask opening for the prior trench etch. Growing an oxide of sufficient thickness may cause mechanical stress as the oxide expands and consumes substrate material. High temperatures are also generally required to grow the oxide.
Another problem with the LOCOS process is that the oxidation rate is generally strongly crystal plane dependent. Because the substrate sidewalls of the trench comprise different crystal planes, the oxide thickness can vary substantially around the trench, causing leakage and other device reliability problems.
After the trench mask is removed, the buried plate of the trench capacitor is typically formed by doping the substrate surrounding the lower portion of the trench. A deposition-free doping technique such as gasphase doping, however, is difficult to use because the dopant (e.g., arsenic) tends to penetrate the LOCOS collar oxide. An alternative is to use a deposited doping layer, such as arsenic silicate glass (“ASG”). This approach, however, generally requires another recess step after the buried plate doping step in order to remove the deposited layer from the collar oxide.
As another example, the collar oxide may be formed using a deposition method, such as tetraethyloxysilane decomposition process (“TEOS process”). In this case, no silicon from the trench sidewalls is consumed because the oxide is deposited instead of being grown. A difficulty with this approach is that the buried plate dopant process, whether deposited or deposition-free, has the same dopant penetration problem as the LOCOS process. That is, the buried plate dopant process is not a self-aligned process.
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented, and technical advantages are generally achieved, by a preferred embodiment of the invention in which at least two insulative layers are used for the isolation collar of a trench device. The first layer is preferably an oxide formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer formed on the oxide layer. The multiple layers function as the isolation collar for the trench, and generally avoid the problems associated with prior art methods of using a single oxidation process alone.
In accordance with a preferred embodiment of the present invention, a method of forming an isolation collar in a deep trench on a semiconductor substrate comprises forming a conformal oxide layer on an interior surface of the trench; filling a lower portion of the trench with a mask layer, thereby masking a lower sidewall and bottom of the oxide layer and leaving an upper sidewall of the oxide layer unmasked; forming a conformal insulation layer on the oxide layer upper sidewall and on an upper surface of the mask layer; anisotropically etching the insulation layer to remove horizontal sections of the insulation layer, thereby leaving an upper sidewall of the insulation layer in the trench adjacent the oxide layer upper sidewall; removing the mask layer from the trench to expose the lower sidewall and bottom of the oxide layer; and removing the lower sidewall and bottom of the oxide layer from the trench to expose the substrate surface in the lower portion of the trench.
In accordance with another preferred embodiment of the present invention, a method of forming a dynamic random access memory (DRAM) integrat
Gruening Ulrike
Kudelka Stephan
Michaelis Alexander
Schroeder Uwe
Tews Helmut Horst
Infineon - Technologies AG
Kennedy Jennifer M.
Niebling John F.
Slater & Matsil L.L.P.
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