Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-16
2002-06-11
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
06405336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a system for generating a test pattern of an LSI tester, and more specifically to a method and a system for generating an LSI tester pattern used when a final test of a semiconductor integrated circuit is executed by an LSI tester.
2. Description of Related Art
In a fabricating process of the semiconductor integrated circuit, first, a logic circuit is designed in accordance with a required specification of a product, a test pattern is prepared for the logic circuit, and a logic simulation is executed using the test pattern prepared, in order to verify the function and the operation timing of the logic circuit.
Furthermore, before an actually fabricated semiconductor integrated circuit is shipped as a product, a final test of the actually fabricated semiconductor integrated circuit is executed by use of an LSI tester by using the same pattern as the test pattern used in the simulation. In the LSI tester, an output signal outputted from the semiconductor integrated circuit is compared with an expected output value verified in the simulation when the same test pattern is applied. Thus, it is verified that the semiconductor integrated circuit has the same function as that of the designed logic circuit and operates at the same timing as that of the designed logic circuit.
However, there are cases in which when the final test was performed by the LSI tester, the output signal of a non-defective semiconductor integrated circuit is not consistent with the expected output value corresponding to the test pattern, with the result that the non-defective semiconductor integrated circuit is deemed as being a defective. One of causes for this problem is considered to be a tester skew which is a timing difference between signals supplied from pins of the LSI tester to input terminals of the semiconductor integrated circuit.
The LSI tester operates to supply a test pattern to the semiconductor integrated circuit at a designated output timing, namely, at the same timing as that in the simulation. Actually, however, because of an insufficient precision of the LSI tester and a delay of a signal on a tester board, the timing of signals supplied from the LSI tester to the semiconductor integrated circuit, has a skew on the order of several 100 picoseconds to several nanoseconds. Therefore, even if it is intended to supply signals to input terminals of the semiconductor integrated circuit at the same timing, these signals are not necessarily simultaneously inputted to the semiconductor integrated circuit, so that a variation of the input timing occurs within the range of the skew width.
Now, this problem will be further described with reference to
FIG. 1
, which is a logic diagram illustrating a part of a logic circuit in the semiconductor integrated circuit. The shown partial logic circuit includes external terminals
1
,
2
and
3
, combinational circuits
5
A,
5
B,
5
C and
5
D and flipflops (F/F)
6
A and
6
B which are sequential unitary circuits. A data signal is supplied from the external terminal
1
through the combinational circuit
5
A to a data input D of a second stage flipflop
6
B. Another data signal is supplied from the external terminal
2
through the combinational circuit
5
B to a data input D of a first stage flipflop
6
A. A clock signal is supplied from the external terminal
3
through the combinational circuit
5
C to a clock input C of the first stage flipflop
6
A.
A data signal is supplied from a data output Q of the first stage flipflop
6
A through the combinational circuit
5
D to a clock input C of the second stage flipflop
6
B.
In order for the flipflop to normally operate, the data signal must become definite a setup time or more before the changing timing of the clock signal, and must be held for a time which starts from the changing timing of the clock signal and which is not shorter than a hold time. If the clock signal and the data signal fulfills this relation, the operation of the flipflop is stable. However, if this relation is not fulfilled, the output of the flipflop is not settled either at a high level or a low level. This condition is called that the clock signal and the data signal “contend” with each other. Therefore, the input timing of the clock signal and the input timing of the data signal must be made to fulfill the above mentioned relation.
In the simulation, if the above relation is fulfilled, an expected value error does not occur in an external output of the semiconductor integrated circuit. However, when the semiconductor integrated circuit is actually tested by the LSI tester, it is in some cases that the above relation is not fulfilled because of the tester skew so that the output of the flipflop does not become definite, and it is in an extreme case that the value should be rightfully latched after the data signal has changed but the value is actually latched before the data signal changes, or alternatively, the value should be rightfully latched before the data signal changes but the value is actually latched after the data signal has changed, with the result that the output value of the flipflop is inverted. If this condition is propagated to the external of the LSI, the non-defective product is discriminated as being defective.
In order to avoid this problem in the prior art, a timing-shifted pattern is prepared by shifting the timing of the pattern change on the input terminals on the basis of the test pattern used in the LSI tester while considering the tester skew, and a logic simulation is executed by using the timing-shifted pattern thus prepared, so as to verify possibility that a trouble in measurement occurs due to the tester skew.
Now, his prior art method will be described with reference to
FIG. 2
, which is a flow chart illustrating the steps of the prior art method for discriminating the test pattern in order to avoid the trouble in measurement due to the tester skew.
First, a plurality of external terminals concurrently changing the input test patterns (namely, their signal levels) are retrieved from the test pattern for the logic simulation (step S
51
). The changing timing of the input test patterns (namely, their signal levels) on the external terminals retrieved is shifted from each other, so that a pair of simulation patterns are generated (step S
52
).
Here, referring to
FIGS. 3 and 4
, an upper half of these figures shows that the input test patterns (namely, signal levels) on external terminals
1
to
4
concurrently change, and a lower half of these figures shows that, by using the input test pattern on the external terminal
1
as a reference, the changing timing of the input test patterns on the external terminals
2
to
4
are shifted in order by a pattern period T. Specifically, the example of
FIG. 3
shows that the changing timing of the input test patterns on the external terminals
2
to
4
are delayed in order from the changing timing of the input test pattern on the external terminal
1
. On the other hand, the example of
FIG. 4
shows that the changing timing of the input test patterns on the external terminals
2
to
4
are advanced in order from the changing timing of the input test pattern on the external terminal
1
.
By using each of the two simulation test patterns
1
and
2
thus prepared, a delayed simulation is executed (step S
53
and step S
54
), and the result of each simulation is examined to check whether or not an error exists in an expected value of output terminals, for the purpose of verifying the skew between the input terminals (step S
55
). If no error is fount out in each of the two simulations (OK), it is discriminated that there is no possibility that a trouble occurs due to the tester skew, and therefore, the original test pattern can be used in the LSI tester with no modification.
If the expected value error occurs, since there is possibility that a trouble occurs due to the tester skew, it is necessary to modify the test pattern. In this case, however, it is not po
Scully Scott Murphy & Presser
Ton David
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