Radiant energy – Inspection of solids or liquids by charged particles – Electron probe type
Reexamination Certificate
2000-11-02
2002-05-14
Anderson, Bruce (Department: 2881)
Radiant energy
Inspection of solids or liquids by charged particles
Electron probe type
C250S492200, C250S492230, C250S252100, C324S1540PB, C324S765010, C438S494000, C438S014000
Reexamination Certificate
active
06388253
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for monitoring and controlling processing carried out on a semiconductor substrate, and more particularly for controlling critical dimensions (CDs) of features formed on the semiconductor substrate through feedback and feed-forward of information gathered during in-process inspection of the features. The invention has particular applicability for in-line inspection of semiconductor wafers during manufacture of high-density semiconductor devices with submicron design features.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
One important process requiring careful inspection is photolithography, wherein masks are used to transfer circuitry patterns to semiconductor wafers. Typically, a series of such masks are employed in a preset sequence. Each photolithographic mask includes an intricate set of geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (i.e., a photoresist layer) which has been previously coated on a layer, such as a polysilicon or metal layer, formed on the silicon wafer. The transfer of the mask pattern onto the photoresist layer is conventionally performed by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the mask to expose the photoresist. The photoresist is thereafter developed to form a photoresist mask, and the underlying polysilicon or metal layer is selectively etched in accordance with the mask to form features such as lines or gates.
Fabrication of the mask follows a set of predetermined design rules set by processing and design limitations. These design rules define the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. The design rule limitation is referred to as the critical dimension (“CD”), defined as the smallest width of a line or the smallest space between two lines permitted in the fabrication of the device. The CD for most ultra large scale integration applications is on the order of a fraction of a micron.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, inspection and measurement of surface features' CD, as well as their cross-sectional shape (“profile”) are becoming increasingly important. Deviations of a feature's CD and profile from design dimensions may adversely affect the performance of the finished semiconductor device. Furthermore, the measurement of a feature's CD and profile may indicate processing problems, such as stepper defocusing or photoresist loss due to over-exposure.
Thus, CD and profile values, and the variation of feature CD from design dimensions, are important indicators of the accuracy and stability of the photoresist and etch processes, and “CD control” to reduce such variation is an important part of semiconductor processing. CD control necessarily involves monitoring and adjusting both the photolithography and etch processes to address CD variations from field to field (FTF) within a wafer, from wafer to wafer (WTW) and from lot to lot (LTL). Among FTF, WTW and LTL variation, FTF and LTL are dominant variation components, while WTW typically counts for less than 10% of the total CD variation. FTF variation is generally determined by process tool performance, such as photoresist coating and baking uniformity, stepper or scanner stage leveling, and etch micro-loading uniformity. On the other hand, LTL variation is generally determined by process stability, including process equipment stability.
Because of the extremely small scale of current CD's, the instrument of choice for measurement and inspection of surface features produced by photolithographic processing is a scanning electron microscope (SEM) known as a “critical dimension scanning electron microscope” (CD-SEM). Although conventional SEM's are useful for measuring CD's, they generally do not provide immediate feedback to the photolithography process to reduce LTL variations, and the results of conventional inspections are not typically used to adjust subsequent etch processing. Furthermore, conventional CD-SEMs cannot provide an adequately detailed direct image or measurement of feature profiles. Still further, conventional methods of direct inspection of feature profiles are destructive to the sample under inspection, are time-consuming, or both.
There exists a need for a simple, cost-effective methodology for fast and meaningful identification and correction of lot to lot CD variation without significantly reducing production throughput.
SUMMARY OF THE INVENTION
An advantage of the present invention is the ability to reduce lot to lot CD variations in semiconductor wafers without reducing production throughput, by utilizing information gathered during in-process inspection of the wafers.
According to the present invention, the foregoing and other advantages are achieved in part by a method of controlling the processing of a semiconductor wafer, which method comprises performing a first process on the wafer and obtaining characteristics of a target feature on the wafer formed using the first process. A set of process parameter values for a second process is determined based on the target feature characteristics, and the second process is then performed on the wafer based on the second process parameter values. Additionally, a set of process parameter values is determined for the first process responsive to the target feature characteristics, and the first process is performed on another semiconductor wafer responsive to the first process parameter values.
Another aspect of the present invention is an apparatus for carrying out the steps of the above method.
A still further aspect of the present invention is a computer-readable medium bearing instructions for controlling the processing of a semiconductor wafer, the instructions, when executed, being arranged to cause one or more processors to perform the steps of the above method.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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Applied Materials Inc.
Bach Joseph
Mcdermott Will & Emery
Wells Nikita
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