Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-06
2002-04-02
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S236000
Reexamination Certificate
active
06365448
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to the structure and fabrication of gated lateral bipolar transistors.
2. Description of the Related Art
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits require the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface area on a silicon chip/die that can be dedicated to a single transistor dwindles. It is desirable then, to construct transistors which occupy less surface area on the silicon chip/die.
Integrated circuits are predominantly designed with one of two types of transistors. These two types are metal-oxide semiconductor (MOS) transistors and bipolar junction transistors (BJTs). MOS transistors are prevalent in integrated circuit technology because they generally demand less power than their counterpart, bipolar transistors. Bipolar transistors, on the other hand, also possess certain advantages over MOS transistors, such as speed. Therefore, attempts have been made to combine the technological designs of bipolar transistors and MOS transistors in an effort to maximize the benefits of both transistor types.
Various types of lateral MOS transistors have been historically described and utilized in complementary metal oxide semiconductor (CMOS) technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal oxide semiconductor (BiCMOS) technologies. Recently newer devices have been developed which have both MOS and bipolar characteristics and functionality. A more careful distinction is made between the different types of transistor action possible in the newer devices. These newer devices include the so-called “gate-body” connected MOS transistor and the “gated lateral” bipolar transistor. The term gate-body connected transistors is used to describe vertical or other device structures where the body of the MOS transistor also serves as the base of a bipolar transistor but each device functions separately as a normal transistor and MOS transistor action is dominant. A voltage applied to the gate region of the structure is also directly input into the body of the semiconductor material. This results in reducing the threshold voltage of the MOS transistor.
In a gated lateral transistor, not only the structures but also the operation is merged and most current flows along the surface under the gate in either MOS or bipolar operation. At low gate voltages around threshold (V
t
) the gated lateral bipolar transistors can act as gate-body connected MOS transistors. At higher input voltages, V
t
or more, the bipolar action can dominate and they are more appropriately described as gated lateral bipolar transistors.
One problem with conventional designs of gate-body and gated lateral transistors is that they use up precious die space in the fabrication of integrated circuits. What is needed is a structure which can offer merged transistor action, yet also conserve space on the chip's surface. Structures which conserve space contribute toward higher density fabrication, and increased utility for integrated circuits. It is desirable that any improved configuration for transistor structure be adaptable to present integrated circuit design. Thus, it is an objective to uncover newly configured transistors which conserve chip space and which can be employed in conventional digital circuit technology.
SUMMARY OF THE INVENTION
In one embodiment, a gated lateral bipolar transistor is provided. The gated lateral bipolar transistor is a single crystalline semiconductor structure. The structure has an upper surface and opposing sidewall surfaces. The single crystalline semiconductor structure has a retrograded and more highly doped bottom layer/well. There is a source/emitter region and a collector/drain region on the upper surface. A dielectric layer is formed on the upper surface as well as on the opposing lower sidewall surfaces of the single crystalline semiconductor structure. A gate is located above the dielectric layer, above the upper surface of the single crystalline semiconductor structure. Conductive sidewall members are included which couples to the gate. This sidewall member additionally couples to the opposing sidewall surfaces. The gated lateral bipolar transistor gives both BJT and MOS action.
In another embodiment, a gated lateral bipolar transistor is formed on a semiconductor substrate. The transistor has a first layer of semiconductor material extending outwardly from the substrate. The first layer of semiconductor material includes an upper surface and has opposing sidewall surfaces. There is a second layer of semiconductor material formed on and extending outwardly from the upper surface of the first layer of semiconductor material. Like the first layer of semiconductor material, the second layer of semiconductor material has opposing sidewall surfaces and an upper surface. On its upper surface, the second layer of semiconductor material has a source/emitter region and a collector/drain region. A dielectric layer is formed over the upper surface of the second layer of semiconductor material and also over the opposing sidewall surfaces of both the first and second layers of semiconductor material. A gate is formed on this dielectric layer. And, a conductive sidewall member is disposed adjacent to portions of the dielectric layer. The conductive sidewall member also couples to portions of the first layer of semiconductor materials.
In another embodiment, the gated lateral bipolar transistor is formed on an insulator layer formed on a p+ silicon material substrate. A first layer of semiconductor material extends outwardly from the insulator layer and has opposing sidewall surfaces and an upper surface. A second layer of semiconductor material extends outwardly from the upper surface of the first layer of semiconductor material along with opposing sidewall surfaces. An upper surface of the second layer of semiconductor material is provided with a source/emitter region and a collector/drain region. A dielectric layer formed on the upper surface of this second layer of semiconductor material, and likewise on the opposing sidewall surfaces of both the first and second layers of semiconductor material. There is again a gate formed on the dielectric layer. Conductive sidewall members are disposed adjacent to the opposing sidewall surfaces. The conductive sidewall members additionally couple to the gate. The conductive sidewall members have electrical contact to portions of the first layer of semiconductor material. In this embodiment, the insulator layer is formed of an oxide layer, and the first layer of semiconductor material is more highly doped than the second layer of semiconductor material. The conductive sidewall members are formed of polysilicon. This gated lateral bipolar transistor gives both BJT and MOS action beneath the gate and is adapted to operate at a voltage input no greater than 1.5 volts.
The present invention also provides a method of fabrication for a gated lateral bipolar transistor. In one embodiment, the method of fabrication includes forming a planar body that extends outwardly from a semiconductor substrate. The planar body is formed to include a top surface and a pair of sidewalls. A dielectric layer is formed on the top surface as well as on the pair of sidewalls. A gate is then formed on the dielectric layer. Forming the gate includes disposing the gate adjacent to the top surface and to the pair of sidewalls of the planar body. A source/emitter region is implanted into the top surface of the planar body. A drain/collector region is also implanted into the top surface. The method of fabricating the gated lateral bipolar transistor includes providing for both bipolar junction transistor (BJT) and metal-oxide semiconductor (MOS) type conduction in the planar body. The method includ
Forbes Leonard
Noble Wendell P.
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