Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-03
2002-07-02
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C712S227000
Reexamination Certificate
active
06415409
ABSTRACT:
BACKGROUND OF THE INVENTION
In the prior art, an electronic system for testing chips is disclosed in U.S. Pat. No. 5,390,129. This prior art system is assigned to Unisys Corporation, who also is the assignee of the present invention.
A simplified block diagram of the prior art chip testing system is shown in
FIG. 2
of patent '129. That system includes a computer
50
which is coupled via a time-shared bus
52
to a plurality of driver boards
100
; and each driver board
100
is coupled to a respective burn-in board
500
which holds several integrated circuit chips that are to be tested.
In operation, the computer
50
sequentially sends each driver board
100
a separate set of test data patterns that are used to test the chips. These test data patterns are stored on each driver board in a large SRAM which is shown in
FIG. 3
by reference numeral
107
and is shown in greater detail in
FIG. 9
by reference numeral
145
. Which particular driver board receives and stores the test data patterns at any one time is determined by an address circuit
100
A that is on the driver board, and is shown in the
FIG. 2
block diagram.
After the test data patterns are stored in the SRAM
145
on all of the driver boards
100
, then the chips on all of the burn-in boards
500
can be tested in parallel. To do that, the test patterns are concurrently read from all of the SRAMs and sent through respective output driver modules
164
, as shown in
FIG. 14
, to the chips on all of the burn-in boards
500
.
One particular feature of the chip testing system in patent '129 is that each burn-in board includes an ID code which identifies the types of chips that are to be tested on the board. That ID code is sensed by the driver board
100
and sent to the computer
50
; and in response, the test data patterns which the computer
50
sends to the driver board are tailored to the ID code that is sensed.
However, the chip testing system in patent '129 also has some major limitations which are imposed by the
FIG. 2
architecture. For example, the computer
50
is the sole source of the test data patterns for all of the driver boards
100
. Consequently, the speed of operation of the chip testing system is limited because the computer
50
can only send the test data patterns to a single driver board at a time over the bus
52
.
Another limitation of the chip testing system in patent
129
is that each driver board
100
always tests all of the chips on a burn-in board
500
concurrently. However, each burn-in board inherently has a limit on the total amount of power which the chips on the board can dissipate. Thus, in order to keep the total power dissipation on each burn-in board
500
below a certain limit, the total number of chips on each burn-in board must be decreased as the maximum power dissipation per chip increases.
Still another limitation of the chip testing system in patent '129 is that the stored test data patterns in a large SRAM
145
on each driver board can make very inefficient use of the SRAM memory cells.
FIG. 9
of patent '129 shows that each SRAM
145
receives nineteen address bits and has eight data output bits; and thus the SRAM
145
on each driver circuit has eight million memory cells. But, certain types of chips are tested by sending them sequences of serial bit streams that vary in number with time. Thus, if an SRAM
145
sends four bit streams during one time interval and sends only two bit streams during other time intervals, then half of the SRAM is wasted when the two bit streams are being sent.
To address the above problems with the chip testing system of patent '129, the present inventors filed three U.S. patent applications on Aug. 31, 1999 which are identified as follows:
1. U.S. Ser. No. 09/386,946 entitled “An Electronic System for Testing Chips Having A Selectable Number Of Pattern Generators That Concurrently Broadcast Different Bit Streams To Selectable Sets Of Chip Driver Circuits”;
2. U.S. Ser. No. 09/387,197 entitled “A Program Storage Device Containing Instructions That Are Spaced Apart By Unused Bits That End On Word Boundaries And Which Generate Chip Testing Bit Streams Of Any Length”; and,
3. U.S. Ser. No. 09/386,945 entitled “An Electronic System For Testing A Set Of Multiple Chips Concurrently Or Sequentially In Selectable Subsets Under Program Control To Limit Chip Power Dissipation”.
Each of the above patent applications include the same set of
FIGS. 1-12
, and they each have the same Detailed Description. Also, each of the above patent applications has a separate set of claims which cover different aspects of the chip testing system that is disclosed.
The invention as claimed in U.S. Ser. No. 09/386,946 addresses the limitation in patent '129 regarding speed of operation. In particular, those claims cover a system for testing integrated circuit chips which is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams, word by word, from its respective memory; and it sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel.
Since all the chip driver circuits which are coupled to one separate bus receive the words of the bit streams simultaneously from one pattern generator, the speed of operation is increased over the prior art. Also, since all of the pattern generators send different bit streams at the same time on separate busses, the speed of operation is further increased over the prior art.
In U.S. Ser. No. 09/387,197, the invention as claimed addresses the limitations of patent '129 regarding inefficient use of memory to store the test data patterns. In particular, these claims cover a system for testing integrated circuit chips which is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary.
If the code indicates that the number of bit streams in a set is only one, then the one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more that one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. Consequently, the only memory cells that are wasted are those which store the unused bits after each bit stream. But, those unused bits are insignificant in number when each of the bit streams is long.
In U.S. Ser. No. 09/386,945, the invention as claimed addresses the limitations of patent '129 regarding total power dissipation by the chips which being tested on the burn-in board. In particular, those claims cover a system for testing integrated circuit chips which is comprised of a signal generator that generates a clock signal; and a control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and a means in the control circuit selects particular outputs in response to the commands and passing the clock signal from the first input to only the selected outputs
All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested. Thus, in response to the programmable commands, the clock signal can be sent se
Barr Timothy Allen
Conklin Robert David
Rhodes James Vernon
Fassbender Charles J.
Rode Lise A.
Starr Mark T.
Tu Christine T.
Unisys Corporation
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