Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-01
2002-04-30
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S225000, C438S227000, C438S228000, C438S239000, C438S241000, C438S297000, C438S439000, C438S444000
Reexamination Certificate
active
06380018
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device of the CMOS type, and more particularly relates to a semiconductor device of the CMOS type in which a DRAM element and logic element are formed on the same substrate, and method for production thereof.
2. Description of the Related Art
Recently, in seeking to create a more compact and rapid LSI, developments have advanced in dual-mounted DRAM/logic technology in which a DRAM element and logic element are formed on the same substrate. That the DRAM element and logic element are formed on the same substrate has advantages. This is because a large number of wires can be formed between the DRAM element and the logic element within the LSI. In other words, the rate of data transmission can be readily increased, for example graphic processing performance can be improved. For this reason, the field of application is widening into the graphic accelerators for image processing.
In general, there are large differences in the production processes for a semiconductor device for a DRAM and a semiconductor device for logic unit. Even when comparing methods of element separation for example, there are differences between those for DRAM elements and those for logic elements.
Normally, as shown in
FIGS. 4 and 5
, methods for selective oxidation (referred to as LOCOS
1
and LOCOS
2
herein below) is used in element separation of DRAM elements.
Here, LOCOS is an acronym of “Local Oxidation of Silicon”. First, a brief description of LOCOS
1
will be given with reference to FIG.
4
.
As shown in FIG.
4
(
a
), a thin oxide film
52
and Si
3
N
4
film
53
are formed, in that order, on the P-type semiconductor substrate
1
.
As shown in FIG.
4
(
b
), the Si
3
N
4
film
53
and thin oxide film
52
are selectively removed by a widely known technique of photoetching. Then, using the Si
3
N
4
film
52
as a mask, selective oxidation is performed, and a separation oxide film
54
for the purpose of element separation is formed. Following this, the elements are separated and LOCOS-
1
completed by the removal of the Si
3
N
4
film
53
and thin oxide film
52
, as shown in FIG.
4
(
c
).
There are problems in that along with a size-reduction of the DRAM element, when a separation oxide film
54
is formed by LOCOS-
1
, there are problems in that the interval (pitch) between the element separation region and element formation region cannot be reduced due to the presence of what are known as bird beaks in which the oxide film protrudes in the lateral direction. As a strategy to overcome this problem, and to suppress the spread of oxidation to the element formation region, practitioners have come to use LOCOS-
2
in which a polysilicon film is placed below the Si
3
N
4
film and the birds beak absorbed in this area. A brief description of LOCOS-
2
will be given using FIG.
5
.
As shown in FIG.
5
(
a
), a thin oxide film
65
, polysilicon film
66
, and Si
3
N
4
film
67
are formed, in that order, on a P-type semiconductor substrate
61
.
As shown in FIG.
5
(
b
), the Si
3
N
4
film
67
is selectively removed by the conventional technique of photoetching, and, using the Si
3
N
4
film
67
as a mask selective oxidation performed, and a separation oxide film
68
is formed. Following this, the separation oxide film is formed as shown in FIG.
5
(
c
), and LOCOS-
2
completed by removal of the Si
3
N
4
film
67
, polysilicon film
66
, and thin oxide film
65
.
Meanwhile, LOCOS-
1
and LOCOS-
2
have conventionally been used in the element separation of logic elements. Accompanying the change to gate lengths on the half-micron scale, however, has seen the introduction of the use of LOCOS-
3
. LOCOS-
3
is a method in which, following slight preparatory digging of the semiconductor substrate, the area which has been dug is selectively oxidized. The object of LOCOS-
3
is to suppress the level-differences which occur as a result of the oxide film. This is because, where there are level-differences occurring in the surface of the substrate in which a separation oxide film has been formed, and where a photoresist acting as a mask has been coated on, the thickness of the photoresist film is not uniform. Where the thickness of the photoresist is non uniform in this way, the thickness of lines of DRAM or other elements formed in the lithography process which follows are not uniform. This is referred to as the standing wave effect. For this reason, LOCOS-
3
, a method which allows separation oxide films with few level-differences has come into use. A brief description of LOCOS-
3
will be given using FIG.
6
.
First, as shown in FIG.
6
(
a
), a thin oxide film
79
, and Si
3
N
4
film
80
are formed, in that order, on a P-type semiconductor substrate
71
.
As shown in FIG.
6
(
b
), the Si
3
N
4
film
80
, thin oxide film
79
, and part of the semiconductor substrate
71
to the required depth, are selectively removed by photoetching. With the Si
3
N
4
film
80
as a mask, selective oxidation is then performed, and a separation oxide film
81
formed. Following this, element separation is carried out as shown in FIG.
6
(
c
), and LOCOS-
3
is completed by removal of the Si
3
N
4
film
80
and thin oxide film
79
.
As described above, in LOCOS-
1
, LOCOS-
2
, and LOCOS-
3
, element separation is performed using the separation oxide films from the selective oxidization. Generally however, the LOCOS methods are accompanied by the formation of large level-differences on the surface of the semiconductor substrate as a result of volume expansion which occurs in the selective oxidization. A major feature of LOCOS-
3
lies in that there is a preparatory digging out of the silicon substrate by photo-etching to prevent the occurrence of these large level-differences.
In each instance of the prior art described above, however, the following drawbacks exist. That is to say, LOCOS-
1
and LOCOS-
2
are appropriate for the element separation of DRAM elements. Where there is element separation of logic elements formed at a level of about the half-micron scale using LOCOS-
1
or LOCOS-
2
, however, problems arise in that it is difficult to control gate length dimensions. This is because the standing wave effect in lithography cannot be controlled.
Moreover, LOCOS-
3
is appropriate for the element separation of logic elements. When LOCOS-
3
is applied to the element separation of DRAM elements, however, problems arise in that, as a result of the digging out of the semiconductor substrate, defects occur in the semiconductor substrate, and diffusion layer leakage increases. Generally, in order to preserve data the diffusion layer leakage is set lower in LSI for DRAM than in LSI for logic. For this reason, the properties of LSI for DRAM deteriorate using the LOCOS-
3
method in which the semiconductor substrate is dug out.
In addition, LSI for DRAM and LSI for logic have hitherto, been designed and produced using different production techniques. These production techniques are already established. Here, there are different separation oxide films formed by different production techniques. More specifically, the shape and spread of bird beak structures differ. For this reason, when a separation oxide film is formed by one of the methods, (either LOCOS-
1
or LOCOS-
3
for example), an increase or decrease in the area of the element formation region is induced. The significance of this is that an increase or decrease in the level of LSI integration and/or capacity occurs, and that one of the design assets of LSI for DRAM or logic units already established becomes unusable without further modification.
Where LSI with dual-mounted DRAM/logic units are produced, in order to make good use of the respective LSI design assets for DRAM and for logic of the prior art, the design rules for DRAM and for logic elements of the prior art must be used.
Similar technology to the present invention is disclosed in Japanese Laid Open Patent Application No. H3-262154. In this LSI different types of separation oxide film are fo
Jr. Carl Whitehead
McGinn & Gibb PLLC
NEC Corporation
Thomas Toniae M.
LandOfFree
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