Developer soluble dyed BARC for dual damascene process

Details Developer soluble dyed BARC for dual damascene process Developer soluble dyed BARC for dual damascene process

2000-11-06

2002-09-24

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S622000, C438S623000, C438S624000, C438S637000, C438S638000

Reexamination Certificate

active

06455416

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to employing a developer soluble dyed film to improve the formation of trenches.
BACKGROUND ART
Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and a plurality of dielectric and conductive layers formed thereon. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Such interconnection lines, made of metal interconnect materials, generally constitute a limiting factor in terms of size (width) and various functional characteristics of the integrated circuit. As such, there exists a need to provide a reliable interconnection structure having a small size yet capable of achieving higher operating speeds, improved signal-to-noise ratio and improved reliability.
Using a dual damascene process, semiconductor devices are patterned with several thousand openings for conductive lines and vias which are filled with a conductive metal, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel signal lines of conductive metal in the insulating layers of multilayer substrate on which semiconductor devices are mounted.
Damascene (single damascene) is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings and the pattern is anisotropically etched in the upper half of the insulating layer. This is the via mask step. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. This is the trench mask step. After the etching is complete, both the vias and grooves are filled metal.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Although standard dual damascene offers advantages over other processes for forming interconnections, it has a number of disadvantages and problems. For example, after the trench mask (second mask) is patterned, resist debris undesirably collect in the recently formed vias. The existence of resist debris in the bottom of the vias leads to poor electrical connections, and possible device failure once the integrated circuit is completed.
Another problem associated with formation of the trench/via openings is reflectivity. Reflectivity causes linewidth variations and degrades lithgraphy processing. Especially in processes where transparent layers are employed, and especially in instances where transparent layers are employed over reflective layers, it is difficult to accurately pattern (for example, due to reflectivity concerns) the masks (resist for forming the vias/trenches). As a result of these concerns, antireflection coatings (ARC) or layers may be employed in an attempt to minimize reflectivity.
Yet another problem associated with formation of the trench/via openings is illustrated in
FIGS. 1 and 2
.
FIGS. 1 and 2
demonstrate that even when an ARC is employed over reflective layers, it is difficult to accurately pattern the second mask (resist for forming the trenches). Referring to
FIG. 1
, the results of inaccurately patterning the second mask are shown. In particular, on substrate
10
, a plurality of vias
12
and trenches
14
are shown from top-down perspective. The trenches
14
are not centered directly over vias
12
; instead, the trenches
14
are positioned undesirably to the right of and over vias
12
. The misalignment of trenches
14
relative to vias
12
is caused by reflectivity differences between the ARC, insulator, and/or underlying substrate when exposing the trench mask (resist) to actinic radiation.
Referring to
FIG. 2
, another view of the results of inaccurately patterning the second mask are shown. Over substrate
10
is patterned insulation layer
16
(patterned to contain via
12
) and ARC
18
(also patterned to contain via
12
). However, due to reflectivity differences between ARC
18
and substrate
10
, patterned photoresist
20
(patterned to mask for a trench
14
) is not aligned directly over via
12
. The subsequently formed trench
14
will be positioned undesirably to the right of and over via
12
. Accordingly, even if ARCs are employed in a dual damascene process, the via etch removes a portion of the ARC positioned above the insulation layer, thus leading to potential problems.
Generally speaking, the reflectivity concerns lead to malformed and/or misaligned trenches with relation to the vias. This consequently degrades the electrical properties of the resultant electronic devices. It is therefore desirable to improve the dual damascene process by minimizing poor critical dimension control and/or reflectivity concerns.
SUMMARY OF THE INVENTION
The present invention provides improved dual damascene methods for substrates by using a developer soluble ARC containing a dye to facilitate the formation of trenches directly over (accurately aligned) the previously formed vias. Moreover, by providing an ARC containing a dye in the manner dictated by the present invention, the accumulation of resist contaminants in vias upon developing the trench mask is minimized and/or eliminated.
One aspect of the present invention relates to a method of processing a semiconductor structure, involving the steps of providing a substrate having an insulation layer thereover; forming a first antireflection coating over the insulation layer; patterning a first resist over the antireflection coating; forming a plurality of vias in the insulation layer and the first antireflection coating, the vias having a first width; filling the via with a second antireflection coating, the second antireflection coating comprising a dye and a film forming material; patterning a second resist over the structure and removing the second antireflection coating from the via; forming a trench over the plurality of vias in the insulation layer, the trench having a second width that is larger than the first width; and filling the trench and vias with a conductive material.
Another aspect of the present invention relates to a dual damascene process, involving the steps of depositing a silicon oxynitride layer over a substrate comprising an interlayer dielectric; patterning a first resist over the silicon oxynitride layer; forming a via within the interlayer dielectric and the silicon oxynitride layer; depositing an organic antireflection coating into the via, the organic antireflection coating comprising a dye and a film forming material; depositing a second resist layer over the substrate; developing the second resist layer and simultaneously removing the organic antireflection coating from the via; forming a trench within the interlayer dielectric and the silicon oxynitride layer and directly above the via; depositing a conductive metal into the trench and the via.
Yet another aspect of the present invention relates to a method of forming a trench mask in a dual damascene process, involving the steps of providing a substrate com

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