Method of forming dual conductive plugs

Details Method of forming dual conductive plugs Method of forming dual conductive plugs

2000-11-15

2002-09-03

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S629000, C438S672000

Reexamination Certificate

active

06444520

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to multi-level conductor integrated circuits wherein the conductors are typically fabricated of either a selected metal or polycrystalline silicon. More particularly, this invention is directed to a self-aligned vertical interconnect process which operates to maximize the achievable packing density within the integrated circuit being manufactured.
BACKGROUND OF THE INVENTION
In many fields of integrated circuit manufacturing, such as in the manufacture of dynamic random access memories (DRAMs), the circuits have multiple levels of metal or polysilicon above the surface of the silicon substrate. These multiple levels must be interconnected for proper electrical functioning of the circuit, and so it becomes necessary to provide certain types of electrical connections between the various conductive levels and active or passive devices.
For example, when DRAMs are fabricated it is customary to provide word lines at one level within the integrated circuit structure and bit or digit lines at another level. It then becomes necessary to provide vertical interconnects between the word and bit lines and certain devices such as access transistors fabricated within the silicon substrate.
A typical structure is illustrated in U.S. Pat. No. 5,338,700, entitled “Method of Forming A Bit Line Over Capacitor Array of Memory Cells”, and assigned to Micron Technology, Inc. First, an n-doped polysilicon plug is self-aligned to the transistor gates and word lines. Then, non-self-aligned tungsten plugs are formed to go down to the n-doped plug, the p-doped active area, and the gate interconnect. The tungsten plugs are not self-aligned; accordingly, without careful alignment it is possible that errors in plug placement may result that short the gates and cause electrical errors in the integrated circuit.
A typical method of forming vertical interconnects with a minimum of masking steps is illustrated in U.S. Pat. No. 5,637,525, entitled “Method of Forming a CMOS Circuitry”, and assigned to Micron Technology, Inc.
What is needed is a simpler process for producing low resistance conductive plugs that provide vertical interconnects in a semiconductor structure. Also needed is a process that minimizes deep contacts and improves alignment of etching with respect to the gate with a minimum number of masking and etching steps.
SUMMARY OF THE INVENTION
The present invention provides a method for making a semiconductor device with conductive plugs of different conductivity types in contact with the active areas of a semiconductor substrate and the active layers of devices such as transistors. The protective layer of the semiconductor substrate is selectively removed down to a semiconductor region of one conductivity type and to the protective cap of an active device to provide openings that are subsequently filled with conductive material of a first type such as doped polysilicon. Next, the conductive material and the protective layer are selectively removed down to a semiconductor region of an opposite conductivity type, and through the protective cap to the active layer of the active device to provide openings that are subsequently filled with conductive material of a type different than that of the first conductive material such as refractory metal or doped polysilicon of a different type. The conductive materials are then removed from the surface of the protective layer to provide first, second and third conductive plugs in the openings.
Advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.


REFERENCES:
patent: 4502210 (1985-03-01), Okumura et al.
patent: 4650544 (1987-03-01), Erb et al.
patent: 4727045 (1988-02-01), Cheung et al.
patent: 4764480 (1988-08-01), Vora
patent: 4866009 (1989-09-01), Matsuda
patent: 4884123 (1989-11-01), Dixit et al.
patent: 4960732 (1990-10-01), Dixit et al.
patent: 4987099 (1991-01-01), Flanner
patent: 5037773 (1991-08-01), Lee et al.
patent: 5055427 (1991-10-01), Haskell
patent: 5063175 (1991-11-01), Broadbent
patent: 5066612 (1991-11-01), Ohba et al.
patent: 5204286 (1993-04-01), Doan
patent: 5210053 (1993-05-01), Yamagata
patent: 5243220 (1993-09-01), Shibata et al.
patent: 5244835 (1993-09-01), Hachiya
patent: 5283203 (1994-02-01), Gill et al.
patent: 5334862 (1994-08-01), Manning et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5362666 (1994-11-01), Dennison
patent: 5472912 (1994-12-01), Miller
patent: 5413950 (1995-05-01), Chen et al.
patent: 5429980 (1995-07-01), Yang et al.
patent: 5457065 (1995-10-01), Huang et al.
patent: 5489546 (1996-02-01), Ahmad et al.
patent: 5494841 (1996-02-01), Dennison et al.
patent: 5571733 (1996-11-01), Wu et al.
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5637525 (1997-06-01), Dennison
patent: 5651855 (1997-07-01), Dennison et al.
patent: 5680345 (1997-10-01), Hsu
patent: 5686747 (1997-11-01), Jost et al.
patent: 5759883 (1998-06-01), Kinoshita
patent: 5907788 (1999-05-01), Kasai
Abstract for Japanese application 1-248536 dated Oct. 4, 1989.

Affiliated with

Also associated with

Rating

Method of forming dual conductive plugs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming dual conductive plugs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming dual conductive plugs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2866669