Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-20
2002-05-21
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S210000, C438S532000, C438S592000
Reexamination Certificate
active
06391704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an MDL semiconductor device including a DRAM device having a self-aligned contact hole and a logic device having a dual gate structure.
2. Description of the Related Art
System on a chip design has evolved with the need for high integration, ultra minuteness of various material layer patterns, high performance, and large wafer diameter in the manufacture of semiconductor devices, as well as the demand for various consumer products utilizing such semiconductor devices. With this trend, due to fast development in the semiconductor field, a high performance and high added-value semiconductor device, including a memory logic merged semiconductor device which is a memory semiconductor device and a logic semiconductor device within one chip, is produced. Particularly, a memory logic merged semiconductor device having a dynamic random access memory (DRAM) referred to as a “merged DRAM logic (MDL)” semiconductor device has become popular.
Important issues addressed by the MDL semiconductor device include improvement of DRAM device integration and logic device performance. Recently, a self-aligned contact hole (SAC) technique has been employed for improving DRAM device integration, while a dual-gate structure has been used for improving logic device performance. Here, a dual gate structure means a structure in which respective gates of a complementary MOS transistor are doped with different conductive type impurity ions.
However, when a self-aligned contact hole is used in a DRAM device, it is not easy to dope impurities of different conductive types on the gates of the complementary MOS transistors in the logic circuit. It is preferable to dope impurities of different conductive types on the respective gates to create a high-performance, complementary MOS transistor in a logic circuit. When the respective gates are formed on a DRAM device and a logic device, and a self-aligned contact hole is formed on the DRAM device, a silicon nitride layer is formed for a self-aligned contact process. The silicon nitride layer is formed not only in a DRAM device region but also in the logic device region, such that the process for doping impurities on the gates of the logic device is restricted. To solve this problem, gate patterns are formed on the logic device separately from the DRAM device, and a process for injecting impurity ions is performed twice using respective mask layer patterns. However, in this case, the process is complicated, and production cost is increased due to an increased use of the mask layer patterns.
SUMMARY OF THE INVENTION
To address the above limitations, it is an objective of the present invention to provide a method for manufacturing an MDL semiconductor device including a DRAM device having a self-aligned contact hole and a logic device having a dual gate structure using fewer mask layers.
Accordingly, to achieve the above objective, there is provided a method for forming an MDL semiconductor device including a DRAM device and a logic device on a semiconductor substrate having a DRAM device region and a logic device region according to the present invention, comprising the steps of forming a gate dielectric layer and a gate conductive layer on a semiconductor substrate; forming first and second gate conductive layer patterns in first and second MOS regions, respectively, in a logic device region of the semiconductor substrate; forming first and second gate spacers on the sidewalls of the first and second gate conductive layer patterns; injecting impurity ions of a first conductive type onto the exposed first gate conductive layer pattern and the semiconductor substrate using a first mask layer pattern exposing the first MOS region; injecting impurity ions of a second conductive type onto the gate conductive layer of the exposed DRAM device region, the second gate conductive layer pattern of the logic device region, and the semiconductor substrate using a second mask layer pattern exposing the DRAM device region and the second MOS region; forming a nitride layer which covers the gate conductive layer of the DRAM device region, the first and second gate conductive layer of the logic device region, the first and second gate spacers, and the exposed semiconductor substrate; forming gate conductive layer stacks, in which the gate conductive layer patterns and the nitride layer patterns are sequentially deposited in the DRAM region using a third mask layer pattern which partially exposes the nitride layer of the DRAM device region; forming gate spacers on the sidewalls of the gate conductive layer stacks of the DRAM device region; and forming self-aligned contact pads inter-insulated between the gate spacers of the DRAM device region.
In the present invention, a step of forming an isolation layer, which isolates the DRAM device region from the logic device region and isolates the first MOS region from the second MOS region, may be further included.
It is preferable that the impurity ions of the first conductive type are P-type impurity ions, and that the impurity ions of the second conductive type are N-type impurity ions.
The method may further include forming a metal silicide layer/region on the surface of the semiconductor substrate to be used as an upper portion of the gate conductive layer of the DRAM device region and as an upper portion and a source/drain region of the first and second gate conductive layer patterns of the logic device region.
An oxide layer may be formed before the step of forming the nitride layer. Here, it is preferable that the oxide layer is a high-temperature oxide layer.
The step of forming the gate conductive layer stacks preferably includes a step of forming a fourth mask layer pattern which exposes parts of the nitride layer of the DRAM device region, and a step of etching the nitride layer and the gate conductive layer using the fourth mask layer pattern as an etching mask.
The step of forming the self-aligned contact pads preferably includes the steps of forming an interdielectric layer which covers the gate conductive layer stacks and gate spacers of the DRAM device region, and the nitride layer of the logic device region; forming a fifth mask layer pattern which expose parts of the surface of the interdielectric layer of the DRAM device region; forming a self-aligned contact hole by etching the exposed interdielectric layer using the fifth mask layer pattern as an etching mask, and exposing parts of the surface of the semiconductor substrate of the DRAM device region; removing the fifth mask layer pattern; and forming self-aligned contact pads by filling the self-aligned contact hole with a conductive layer. In this case, it is preferable that the interdielectric layer is formed of a material having an etching selectivity with respect to the nitride layer, for example, the interdielectric layer may be an oxide layer. It is also preferable that the conductive layer is a polysilicon layer.
REFERENCES:
patent: 5998252 (1999-12-01), Huang
patent: 6146994 (2000-11-01), Hwang
patent: 6174807 (2001-01-01), Kizilyalli et al.
patent: 6235574 (2001-05-01), Tobben et al.
Hong Suk-gu
Park Hyung-Moo
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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