Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-28
2002-04-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C365S185040
Reexamination Certificate
active
06376310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a nonvolatile memory device, more particularly, to a fabrication method for improving characteristics and reliability of the nonvolatile memory device.
2. Discussion of the Related Arts
Generally, an effective cell size of a memory cell relating to an integrity of a nonvolatile memory device such as flash EEPROM (Electrically Erasable Programmable Read Only Memory), EEPROM, etc. is determined by two factors.
One of the two factors is a size of a unit cell, and the other is a structure of a cell array. With respect to the memory cell, the minimum cell structure is a simple stacked gate structure.
As the application of a nonvolatile memory has been extended, research and development of the nonvolatile memory such as a flash EEPROM and a flash memory card has been getting more and more attention.
When the nonvolatile semiconductor memory devices such as flash EEPROM, EEPROM, etc., are used as a mass storage media, the most serious problem is the high cost per bit.
Furthermore, for the chip to be used for portable products, low power consumption is required. In order to lower the cost per bit, lots of research in multi bit cells have been conducted.
The integrity of a conventional nonvolatile memory has a one-to-one corresponding relationship to a number of memory cells. On the other hand, a multi bit cell can enhance, remarkably, the integrity of data storage in an identical chip area by storing data of more than one bit per cell instead of reducing the size of the memory cell.
To implement the above-mentioned multi bit cell, each memory cell should be programmed so as to have more than three threshold voltage levels.
For example, in order to store data of two bits per cell, each cell must be programmed so as to have a threshold voltage of four levels (2
2
=4). The four levels of the threshold voltage correspond to logical states 00,01,10,11, respectively.
The most serious problem in the multi level program is that each threshold voltage level has a statistical deviation of about 0.5V from a nominal value.
Accordingly, when the threshold voltage level is precisely adjusted and therefore the deviation in threshold voltage is decreased, the threshold voltage can be programmed with more levels and the number of bits per cell can be increased. In general, in order to reduce deviation in the threshold voltage level, a programming technique which repeatedly performs a programming operation and a verifying operation is used,
In order to program a nonvolatile memory cell to be at a desired threshold voltage level, a series of voltage pulses is applied to the cell.
In order to verify whether or not the threshold voltage of the cell reaches a desired voltage level, a read operation is performed at a time between two adjacent pulses of the voltage pulses. When the result of the verifying operation indicates that the memory cell has reached the desired threshold voltage level, the programming operation is completed,
According to the above-mentioned technique in which the read and verifying operations are repeatedly performed, it is not easy to reduce the error deviation of the threshold voltage caused by a finite pulse width of the program voltage.
Since an algorithm in which the programming and verifying operations are repeatedly performed is implemented in a circuit, the area for a peripheral circuit is enlarged and the program time for the above-mentioned method becomes long.
FIG. 1A
is a cross sectional view showing a structure of a general simple stacked nonvolatile memory device.
FIG. 1B
is a schematic symbol of a general nonvolatile memory cell.
As shown in
FIG. 1A
, a floating gate
3
is formed on a p type semiconductor substrate
1
with a tunneling oxide film
2
between the floating gate and the semiconductor substrate. A control gate
5
is formed on the floating gate
3
. A dielectric film
4
is formed between the control gate
5
and the floating gate
3
.
A n type source region
6
a
and a n type drain region
6
b
are formed in a surface of a p type semiconductor substrate
1
, and are located at both sides of the floating gate
3
. The simple stacked gate nonvolatile memory device having the aforementioned structure has disadvantages as follows: its effective cell size and a coupling constant of the control gate
5
are small, and the coupling constant is reduced as the effective cell size of the nonvolatile memory cell is decreased.
Accordingly, in order to prevent the coupling constant value from being reduced, the dielectric film
4
between the floating gate
3
and the control gate
5
is made of an Oxide Nitride Oxide (ONO) film, but a fabrication process of the ONO film is complicated and requires a high temperature annealing process. As shown in
FIG. 1B
, each nonvolatile memory cell comprises a floating gate
3
, as depicted in
FIG. 1A
, the control gate
5
for controlling an amount of charges to be supplied to the floating gate
3
for programming, and a field effective transistor for reading (or verifying) the amount of the charges supplied to the floating gate
3
.
The field effect transistor comprises a floating gate
3
, a source
6
a,
a drain
6
b,
and a channel region
7
between the drain
6
b
and the source
6
a.
A programming operation of the nonvolatile memory cell having the aforementioned structure is performed by the current flowing between the drain
6
b
and the source
6
a
when the control gate
5
and the drain
6
b
are supplied with voltages high enough to cause programming.
The current is compared with a reference current. When the current is equal to or less than the reference current, a programming completion signal is generated.
A conventional fabrication method of a nonvolatile memory device will be described with reference to
FIG. 2A
to FIG.
2
K.
FIG. 2A
to
FIG. 2K
are cross sectional views showing the processes of a fabrication method of a nonvolatile memory device.
As shown in
FIG. 2A
, an oxide film for separating elements (not shown) is formed on a surface of a p type semiconductor substrate
11
on which a cell region and a peri (or peripheral) region are defined. A cell gate insulation film
12
is formed on an active region of the semiconductor substrate
11
.
In this case, the cell gate insulation film
12
is formed on the entire surface of the semiconductor substrate
11
of the cell region and the peri region.
A first polysilicon layer
13
for floating gate is formed on the cell gate insulation film
12
. The first polysilicon layer
13
is selectively removed by a photolithography technique and etching process so that a plurality of first floating gates
13
a
are formed.
As shown in
FIG. 25
, a first insulation film
14
is formed on the entire surface of the semiconductor substrate
11
including the first floating gate
13
a
and then is selectively removed by a photolithography technique and an etching process so that a plurality of contact holes are formed. Each of the plurality of contact holes is in one to one correspondence with one of the plurality of first floating gates
13
a,
and a first portion of each surface of the floating gates
13
a
is exposed through the corresponding contact hole.
Thereafter, a second polysilicon layer
15
is formed on the semiconductor substrate
11
and at the same time fills the plurality of contact holes.
On the other hand, the first insulation film
14
formed on the peri region of the semiconductor substrate
11
is removed when the contact holes are formed.
As shown in
FIG. 2C
, a second insulation film
16
for controlling an amount of charges of the floating gate is made of an ONO (Oxide Nitride Oxide) film or CVD insulation film on the second polysilicon layer
15
.
As shown in
FIG. 2D
, a third polysilicon layer
17
for forming a control gate is formed on the second insulation film
16
. A cap insulation film is formed on the third polysilicon layer
17
and thereafter selectively removed by a photolithography technique and an etching p
Hynix / Semiconductor Inc.
Vu David
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