Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-08
2002-04-30
Nelms, David (Department: 2878)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S501000
Reexamination Certificate
active
06380020
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device having a device isolation insulating film, and more specifically to a method for fabricating a semiconductor device having a device isolation insulating film having an elevated device reliability, in particular, an elevated device isolation characteristics, by covering each device formation area with an oxidation-resistant film such as a nitride film just until a gate oxidation when different gate oxide films are formed on the same chip.
In general, in a MOS semiconductor device having insulated-gate field effect transistors (MOS transistors) formed on a semiconductor device chip, when a high-breakdown-voltage device-component having a high reliable breakdown voltage and a low-breakdown-voltage device-component needing a high speed operation for a high speed information processing are incorporated in a single semiconductor device chip, the high-breakdown-voltage device-component is required to have a thick gate oxide film and a thick field oxide film. On the other hand, the low-breakdown-voltage device-component is required to have a thin gate oxide film and a thin field oxide film which meet with a microminiaturization and a high speed operation of the semiconductor device.
In the prior art, as a method for forming field oxide films having different film thicknesses and gate oxide films having different film thicknesses on the same substrate in order to fabricate this type of semiconductor device, there was proposed to form a plurality of different gate oxide films by separately forming required oxide films by repetition of a gate oxidation and a wet etching (See Japanese Patent Application Pre-examination Publication No. JP-A-09-036243). Referring to
FIGS. 1A
to
1
E, there are shown diagrammatic sectional views illustrating a process of this prior art method for forming two kinds of gate oxide film.
FIG. 1A
illustrates a condition in which a device isolation oxide film
121
for electrically isolating between device-components is formed on a principal surface of a silicon substrate
300
and a thin oxide film
221
is formed on the surface of the silicon substrate
300
to protect the substrate in an ion implantation. Therefore, the principal surface of the silicon substrate
300
is divided into a plurality of active regions confined by the device isolation oxide film
121
. As shown in
FIG. 1A
, the silicon substrate
300
has a first device formation area
521
needing a first gate oxide film having a large film thickness, as a high breakdown voltage circuit exemplified by a write circuit in an electrically writable read-only-memory (erasable PROM), and a second device formation area
522
needing a second gate oxide film having a small film thickness for a low breakdown voltage since a high breakdown voltage is not needed. The device isolation oxide film
121
can be formed by a LOCOS (local oxidation of silicon) process, or alternatively by a trench isolation forming a trench in a region in which the device isolation oxide film
121
is to be formed, and filling up the trench with an insulating material such as a silicon oxide.
Then, as shown in
FIG. 1B
, the thin oxide film
221
is removed from the surface of the silicon substrate
300
by a first wet etching. Here, the device isolation oxide film
121
is thinned or diminished because of this first wet etching, and becomes a device isolation oxide film
122
which is thinner than the device isolation oxide film
121
.
Thereafter, as shown in
FIG. 1C
, a first gate oxide
222
is formed on the surface of the silicon substrate
300
by oxidation, so that an oxide film is formed on an exposed surface of the silicon substrate
300
in each active region surrounded by the device isolation oxide film
122
.
Next, gate oxide films required in the device formation areas
521
and
522
, respectively, are formed separately from each other. First, as shown in
FIG. 1D
, a resist
421
is deposited and patterned to expose the second device formation area
522
in which a thin gate oxide film is to be formed in the active region, and the first gate oxide film
222
is removed from the surface of the substrate
300
in the second device formation area
522
by a second wet etching using the resist
421
as a mask. In this second wet etching, the device isolation oxide film
122
is further thinned or diminished to become a device isolation oxide film
123
which is thinner than the device isolation oxide film
122
.
Thereafter, as shown in
FIG. 1E
, the resist
421
is removed, and a second gate oxide film is formed by oxidation. In this process, the second gate oxide film formed on the silicon substrate exposed in the active region within the second device formation area
522
constitutes a thin gate oxide film
224
, and an oxide film formed by an additional oxidation carried out on the first gate oxide film
222
remaining on the active region within the first device formation area
521
, constitutes a thick gate oxide film
223
.
With the above mentioned process, the thick gate oxide film
223
and the thin gate oxide film
224
which are required in the device formation areas
521
and
522
, respectively, are formed in the device formation areas
521
and
522
, respectively.
In the above mentioned process for forming the gate oxide films having different film thicknesses by repeating the etching and the gate oxidation in a so called multi-oxide process for the purpose of fabricating a single semiconductor device having different gate oxide film thicknesses on a semiconductor device chip, the device isolation oxide film
121
in the second device formation area
522
is subjected to two wet etchings, one of which is carried out for removing the thin oxide film
221
as shown in
FIG. 1B
, and the other of which is carried out for removing the first gate oxide film
222
, with the result that the device isolation oxide film
121
is thinned to the device isolation oxide film
122
and then further thinned to the device isolation oxide film
123
.
The above mentioned example has two different kinds of gate oxide film, but it could be easily understood to persons skilled in the art that, if the number of the kinds of gate oxide film is increased to three, or four, or more, the number of etchings correspondingly increases, and in a device formation area in which a gate oxide film is formed after a last wet etching, the device isolation oxide film is exposed to a corresponding number of wet etchings.
However, because of a frequent repetition of the oxidation and the wet etching, the following problems have been encountered.
A first problem is that a device isolation leak occurs because implanted ions (particularly, boron) penetrates through a thinned device isolation oxide film and because an inversion layer is created by an interconnection passing directly above the device isolation oxide film. In order to prevent this device isolation leak, it can be considered to increase an initial oxidation amount for the device isolation oxide film in a recess LOCOS, or alternatively to realize the device isolation oxide film by a shallow trench isolation. However, the former is a hindrance to microminiaturization because a diffused layer is destroyed by a bird's beak. The latter aggravates the problem of a step difference which will be described next.
A second problem is that because the thickness of the device isolation oxide film is reduced from an initial oxidized condition by repeated wet etchings, a non-negligible step difference occurs at a boundary between a diffused layer and the device isolation oxide film, with the result that when a gate polysilicon is etched, a polysilicon adversely remains, which causes a short-circuiting.
A third problem is that because of the repetition of the substrate surface oxidation and the wet etching, the impurity concentration in the substrate surface is disturbed, with the result that an electrical characteristics (particularly, a threshold value of a transistor) becomes unstab
Hutchins, Wheeler & Dittmar
NEC Corporation
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