Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-08
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S279000
Reexamination Certificate
active
06376294
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of DRAM integrated circuit devices and specifically to word line strapping methods in DRAM integrated circuit devices.
BACKGROUND OF THE INVENTION
A dynamic random access memory (DRAM) includes a large number of memory cells, each of which can store at least one bit of data. The memory cells are arranged in an array having a number of columns and rows. Memory cells within the same column are commonly coupled to a bit line and memory cells within the same row are commonly coupled to a word line. The memory cells within the array are accessed according to various memory device operations such as read operations, write operations, and refresh operations.
Generally, the word lines are comprised of an N-type polysilicon that contains phosphorous as an impurity (N-doped poly). The resistance of the doped poly word lines is very high as compared to that of a metal and the signal speed decreases due to the resistance of the word lines.
A method of depositing metal layers with a certain interval over the word lines is frequently used and is known as word line strapping. That is, word line strapping skill is commonly used to reduce RC delay as memory cells are accessed through word line gates in DRAM circuits.
However, word lines are often comprised of an overlying SiN hard mask, tungsten silicide (WSi
x
) layer, then doped poly in DRAM circuits. The hard mask is utilized because it can improve self-aligned contact etching window which can increase DRAM cell density.
Based upon the above advantages, the SiN hard mask for self-aligned contact and word line strapping skill for reducing RC delay are always used for DRAM processes and circuit design. In order to make sure word line strapping perfectly contacts on doped poly or WSi
x
, the SiN hard mask must first be opened in advance of the word strapping. This leads to additional fabrication steps, increased fabrication complexity, and increased fabrication cost.
For example, U.S. Pat. No. 5,081,516 to Haskell et al describes word line strapping and dog-bone contacts.
U.S. Pat. No. 5,409,860 to Jeon, U.S. Pat. No. 6,064,589 to Walker, U.S. Pat. No. 5,959,319 to Iwasa, and U.S. Pat. No. 5,583,356 to Yoon et al. describe various word line strapping methods.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention is to provide an improved method to define a poly dog-bone for word line strapping contact at stitch area in embedded DRAM process.
Another object of the present invention is to provide a method of defining a poly dog-bone for word strapping contact without an overlying hard mask.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a stitch region therebetween. A polysilicon layer is formed over the semiconductor structure. A dopant is selectively implanted in the polysilicon region within the DRAM region, and the portion of the stitch region within the DRAM region, to form a doped poly segment, and an undoped poly segment within the LOGIC region, and the portion of the stitch region within the LOGIC region. A hard mask is formed over the doped poly segment and the undoped poly segment and patterned to form at least one patterned first hard mask portion only over the word line doped poly segment within the DRAM region. At least one second mask layer portion is formed over the undoped poly segment within the LOGIC region and at least one third mask layer portion is formed over the doped poly segment in the portion of the stitch region within the DRAM region. The doped poly segment and undoped poly segment are etched to form:
undoped poly periphery logic gate portions within the LOGIC region;
doped poly dog-bone within the portion of the stitch region within the DRAM region; and
doped poly word lines within the DRAM region.
The second and third mask layer portions are stripped to expose the undoped poly periphery logic gate portions and the doped poly dog-bone.
REFERENCES:
patent: 5583356 (1996-12-01), Yoon et al.
patent: 6080620 (2000-06-01), Jeng
patent: 6143604 (2000-11-01), Chiang et al.
Chen Wen-Cheng
Chiang Wen-Chuan
Tzeng Kuo-Chyuan
Wang Chen-Jong
Ackerman Stephen B.
Bowers Charles
Chen Jack
Saile George O.
Stanton Stephen G.
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