Method of forming an embedded memory

Details Method of forming an embedded memory Method of forming an embedded memory

2001-08-07

2002-09-10

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S264000, C438S591000

Reexamination Certificate

active

06448126

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention provides a method of forming an embedded memory, and more particularly, to a method of integrating nitride read only memory (NROM).
2. Description of the Prior Art
In the modern electronics industry, read only memory and a corresponding control device often need to exist in various products simultaneously. In contrast to manufacturing two devices on a single chip, manufacturing the two devices on two separate chips occupies more room and also lifts a production cost. Read only memory (ROM) devices are semiconductor devices for data storage. ROM is composed of a plurality of memory cells and is applied in data storage and memory systems of computers widely today. Read only memory can be classified into mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), nitride read only memory (NROM) and flash ROM, according to a method used for data storage. Once data or information is stored in ROM, the data will not disappear if there is an interruption of power, therefore read only memory is also called non-volatile memory.
Nitride read only memory (NROM) utilizes a silicon nitride isolation dielectric layer as a charge trapping medium. Since the silicon nitride layer is highly dense, hot electrons can tunnel into the silicon nitride layer and be trapped inside it through a MOS transistor. This further forms an inhomogeneous density distribution in order to accelerate a rate of data reading and to avoid leakage current. Because the flash ROM utilizes a floating gate composed of polysilicon or metal to store charges, the flash ROM has an extra gate in addition to a control gate. The former has an advantage of using a simple manufacturing process and incurring a low cost. As the latter one needs to be made with a floating gate-inter-dielectric layer-control gate structure, and the quality of the material in the three-layer structure is very important, it is necessary to coordinate with suitable processes, and this results in a more complex manufacturing process and a higher cost.
Therefore, in U.S. Pat. No. 5,403,764, Yamamoto et al. proposes a method of implanting ROM code into the flash ROM device in the ROM region by utilizing an ion implantation process during a flash ROM manufacturing process, in other words, completing the “read” procedure, then completing the manufacturing process of flash ROM as normal. So, the read only memory can be established in some portion of the flash ROM chip.
Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are schematic diagrams of a process for making a flash ROM chip
10
comprising read only memory
24
, according to the prior art. As shown in
FIG. 1
, the prior art method of forming a flash ROM chip
10
comprising read only memory
24
is to provide a semiconductor wafer
11
comprising a P-type silicon base
12
, then utilize a thermal oxidation process with temperature about 1100° C. and process time about 90 minutes to form a plurality of silicon dioxide (SiO
2
) layers
14
with a thickness of several thousands of angstroms(Å) on a region of the surface of the silicon base
12
not covered by an oxidation-protective film(not shown), such as silicon nitride(Si
3
N
4
). After that, the remaining silicon nitride layer (not shown) is removed and a very thin silicon oxide layer
16
is preserved between the silicon dioxide layers
14
, that is, between each field oxide (FOX) layer. In other words,local oxidation (LOCOS) is utilized to form the isolation in between each transistor, which is completed afterwards.
As shown in
FIG. 2
, an ion implantation process is then performed in the read only memory area
18
of the flash ROM chip
10
. The ion implantation process utilizes an accelerating energy ranging from 40 to 50 keV, and a Boron ion dosage ranging from 1E12 to 3E12/cm
2
to form a first P+ type doping area
22
having ion concentration ranging from 10
16
to 10
17
/cm
3
. The objective of the ion implantation process is to adjust a threshold voltage (Vth) of the first read only memory (not shown) in the read only memory area
18
to a first specific value, so the threshold voltage of the first read only memory (not shown) is adjusted to around 1 V and stores a data “1”.
As shown in
FIG. 3
, a first photolithography process is then performed in order to form a first mask
31
out of the read only memory area
18
and the read only memory (not shown), with a second specific value as its threshold voltage, in the read only memory area
18
. Thereafter, an ion implantation process is performed on the flash ROM chip
10
. The ion implantation process utilizes an accelerating energy ranging from 40 to 50 keV, and a Boron ion dosage ranging from 5E12 to 1E13/cm
2
to form a second P+ type dopant area
32
having a final ion concentration ranging from 10
17
to 10
18
/cm
3
. The objective of the ion implantation process is to adjust the threshold voltage (Vth) of the second read only memory (not shown) in the read only memory area
18
to a second specific value, so the threshold voltage of the second read only memory (not shown) is adjusted to around 7V and stores a data “0”.
As shown in
FIG. 4
, a first polysilicon layer
34
, an interlayer isolation layer
36
composed of silicon nitride or silicon oxide and a second polysilicon layer
38
are then deposited on the flash ROM chip
10
. After that, a second photolithography process is performed in order to form double gates
39
of the first read only memory
24
, the second read only memory
26
and the flash ROM
40
. Although the gate structures of the first read only memory and the second read only memory
24
,
26
are single layered in a general case and the double gates
39
having three layered structure are not required, all of the gates are completed with the same process steps in the prior art method in order to reduce process steps.
As shown in
FIG. 5
, a phosphorous ion implantation process utilizing a third mask (not shown) is performed in order to form an N+ source
41
and an N+ drain
42
at either side of the double gate
39
of the first read only memory and the second read only memory
24
,
26
to complete the manufacturing of the first read only memory and the second read only memory
24
,
26
. Finally, another phosphorous ion implantation process utilizing a fourth mask (not shown) is performed in order to form an N+ source
43
and an N+ drain
44
at either side of the double gate
39
of the flash ROM
40
to complete the manufacturing of the flash ROM
40
. Therefore, not only the read only memories
24
,
26
on the flash ROM chip
10
are written with “0” or “1,” but the flash ROM
40
is also completed by just adding two process steps for threshold voltage adjustment in the standard flash ROM manufacturing process.
Moreover in U.S. Pat. No. 5,966,603, Eitan proposes a method of forming a single chip simultaneously comprising nitride read only memory and a periphery transistor, and points out that the periphery device can have gate dielectric layers with two different thicknesses. He only describes process steps for making the gate dielectric layers with two different thickness briefly. He does not propose a method of protecting the ONO (bottom oxide-nitride-top oxide) dielectric layer in the memory structure in the etching or cleaning process to avoid a top oxide loss problem when making the gate dielectric layers with two different thicknesses.
The prior art methods of making a flash ROM chip up to this point do not disclose any effective methods for resolving the top oxide loss problem. Moreover, the flash ROM is not suitable for being manufactured as a system on chip or an embedded memory, because its cost is high. Therefore, it is very important to develop a method of forming an embedded memory that utilizes cheaper devices together with the flash ROM manufacturing process.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a method of for

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