Method of forming plugs in multi-level interconnect...

Details Method of forming plugs in multi-level interconnect... Method of forming plugs in multi-level interconnect...

1999-11-02

2002-03-05

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S672000, C438S688000

Reexamination Certificate

active

06352916

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to metallization processes used in integrated circuit manufacture. More specifically, the current invention relates to methods of forming a via for electrical communication between multiple levels of interconnects and the devices resulting therefrom.
BACKGROUND OF THE INVENTION
In processing integrated circuits, it is important to be able to establish electrical communication between conductive elements at different locations within a circuit. These elements often take the form of conductive lines or paths known as “interconnects” due to their function of electrically interconnecting circuit nodes. Interconnects at different elevations will be separated by at least one insulation layer, such as an interlayer dielectric. Thus, providing electrical communication between such interconnects will often involve (1) forming the lower interconnect; (2) layering insulation over the lower interconnect; (3) defining an opening, often called a “via,” through the insulation and leading to the lower interconnect; (4) using a conductive material to fill the via, in which case the conductive material may be referred to as a “plug;” and (5) forming the higher interconnect over the plug.
On a larger scale, it should be appreciated that there are often several interconnects at any particular level of a circuit device. Further, one should note that, while one lower level interconnect may need to connect to one higher interconnect at one point, a second lower level interconnect may need to contact a second higher interconnect at a different point. As a result, after the lower level of interconnects have been formed and covered with insulation, a particular pattern of vias are formed in the insulation.
Forming these vias entails etching through the insulation in areas exposed by an overlying patterned mask. Ideally, the etch stops once the lower level of interconnects is reached and before any of the conductive material of that level is etched. In reality, however, the top of the interconnects suffer some degree of etching at the exposure. Polymer may be formed as a result of etching this conductive material. The presence of polymer may interfere with further processing and, therefore, at least one cleaning step may be needed to remove the polymer. Even with cleaning, however, some polymer may remain. The presence of the polymer may then interfere with communication between the plug and the subsequently formed upper interconnect.
Another problem occurs as a result of the constant need in the art to make ever-smaller semiconductor devices to allow a more efficient use of the silicon substrate from which such devices are fabricated. This need requires the widths of features, including vias, to become narrower with each generation of devices. However, a layer of insulation must maintain a minimum vertical distance between upper and lower conductive members; if the insulation between the two such members is too thin, an intolerably high level of capacitance will be generated between the members and interfere with their desired operation. Thus, as circuit dimensions continue to scale down, the width of the via decreases, but its depth, determined by the required thickness of the insulation, must remain generally the same. In other words, the aspect ratio of the via increases as the critical lateral dimensions of devices shrink. Unfortunately, high aspect ratios associated with a via make it difficult to ensure that the via has been completely filled with the conductive plug material. Gaps in the plug will degrade the plug's ability to allow electrical communication between conductive members.
Also of note is the fact that each discrete deposition of one conductor on another represents a potential disruption in continuity of conductive material which, in turn, affects the ability to allow electrical communication. Separate deposition steps may allow contaminants to accumulate between those steps. Further, depositing one kind of conductive material onto a different kind may hamper electrical conductivity. Even assuming that the same type of material is deposited in two separate steps and that contaminants are kept to an absolute minimum, there may still be spaces between the discretely deposited layers that would not exist if the two layers had been deposited as one. All of these factors can adversely affect electrical communication between interconnects at different levels. Specifically, these problems can occur at both the lower level interconnect/plug interface and the plug/higher level interconnect interface.
Thus, there is a need in the art to provide electrical communication between conductive elements while at least reducing the problems discussed above. It would also be desirable to be able to reduce the number of deposition steps needed to provide conductive elements and a connector between them.
SUMMARY OF THE INVENTION
Accordingly, at least some exemplary embodiments of the current invention provide methods of connecting conductive elements and further provide the structures resulting from those methods. In one exemplary embodiment, a trench is etched in a layer of insulation or dielectric, wherein the trench is deep and long enough to accommodate an interconnect as well as a plug or other interlayer electrical connection configured to contact a later-formed interconnect at a higher elevation. The entire trench is filled with conductive material. In an area that is not designated as a plug site, the height of the conductive material is reduced. In an area that is designated as a plug site, the height of the conductive material is retained. The recessed portion of conductive material is then covered with additional insulation. Another interconnect may then be formed over the insulative materials so that it contacts the plug. Other embodiments involve etching a plurality of trenches at one level of a semiconductor device, wherein the trenches are deep enough to accommodate interconnects as well as plug sites anywhere along each trench.
Another exemplary embodiment comprises etching at least one plug/interconnect structure from a continuous layer of metal and then depositing insulation around the structure or structures.
Still another exemplary embodiment comprises using at least one of the processes described above to create multiple levels of interconnects.
Yet other embodiments address the in-process apparatus or final product resulting from these and other processes. Such exemplary embodiments include a conductive structure such as an interconnect that is integral to or is continuous with a plug structure configured to contact a higher interconnect.


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C. Yu, M. Grief, and T. T. Doan, “Submicron Aluminum Plug Process Utilizing High Temperature Sputtering and Chemical Mechanical Polishing,” Conference Proceedings of ULSI—VII, Materials Res. Soc., pp. 519-525, 1992.

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