Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-30
2002-04-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S636000, C438S763000
Reexamination Certificate
active
06372642
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to patterning semiconductor devices with resolution down to 0.12 &mgr;m on a silicon substrate using oxynitride film.
2) Description of the Prior Art
The semiconductor industry's continuing drive toward semiconductor devices with ever decreasing geometries coupled with the reflective property of monocrystalline silicon and polycrystalline silicon (polysilicon, poly) have led to increasing photolithographic patterning problems. Unwanted reflections from the underlying monocrystalline silicon or polycrystalline silicon during the photolithographic patterning process cause the resulting photoresist patterns to be distorted. Diffraction of the light waves used to expose the photoresist during patterning also causes distortion of the resulting patterns.
Organic and inorganic bottom anti-reflective coatings have been attempted on both monocrystalline silicon and polycrystalline silicon to absorb reflected energy and prevent pattern distortion. However, different film thicknesses due to surface topography after coating will cause etching issues, photoresist loss and poor after etch inspection (AEI) dimensions.
Phase-shifting masks have been used to compensate for diffraction and enhance the resolution of photolithographic patterns. A phase shift layer is used to cover one of a pair of adjacent apertures of the pattern mask during exposure. The phase shifting layer reverses the sign of the electric field of its aperture. The distortions of the electric field from adjacent appertures caused by diffraction cancel because they have opposite signs. The phase change is a function of wavelength and thickness of the transparent phase shifting layer. However, phase shifting masks do not prevent distortion from reflections.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,600,165 (Tsukamoto et al.) shows a SiON layer as a bottom ARC over several different structures, including polysilicon, oxide, and silicides.
U.S. Pat. No. 5,639,687 (Roman et al.) shows a Si-rich SiON ARC layer in which thickness (t) is determined as a function of wavelength (&lgr;) and refractive index (n) using the formula t=&lgr;/4n.
U.S. Pat. No. 5,252,515 (Tsai et al.) teaches a process for forming SiON ARC layer with refractive index (n) of between 1.5 and 2.1 by controlling the silane flow rate.
U.S. Pat. No. 4,717,631 (Kaganowicz et al.) shows a SiON passivation layer having a refractive index (n) of between 1.55 and 1.75 at a wavelength (&lgr;) of 632.8 nm.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of patterning semiconductor devices on a silicon substrate using oxynitride films.
It is another object of the present invention to provide a method of patterning semiconductor devices with a resolution down to 0.12 &mgr;m on monocrystalline silicon or polycrystalline silicon.
It is yet another object of the present invention to provide a method of patterning semiconductor devices using both patterned structure and optical properties of oxynitride to acheive resolution down to 0.12 &mgr;m.
To accomplish the above objectives, the present invention provides a method for fabricating and patterning semiconductor devices with a resolution down to 0.12 &mgr;m on a substrate structure (
10
). The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrystalline silicon or polycrystalline silicon. A silicon oxynitride layer (
16
) is formed on the substrate structure (
10
). Key characteristics of the oxynitride layer include: a refractive index of between about 1.85 and 2.35 at a wavelength of 248 nm, an extinction coefficient of between 0.45 and 0.75 at a wavelength of 248 nm, and a thickness of between about 130 Angstroms and 850 Angstroms. A photoresist layer (
20
) is formed over the silicon oxynitride layer (
16
) and exposed at a wavelength of between about 245 nm and 250 nm; whereby during exposure at a wavelength of between 245 nm and 250 nm, the silicon oxynitride layer (
16
) provides a phase-cancel effect, and acts as an inorganic anti-reflective coating, absorbing reflected light energy.
The present invention provides considerable improvement over the prior art. The absorptive properties of the oxynitride layer (
20
) reduce the amount of reflected energy, thereby reducung pattern distortion. A key advantage of the present invention is that during exposure, the silicon oxynitride layer (
16
) also provides a phase-cancel effect. The reflected light is out of phase with and cancels the diffracted light energy, further reducing pattern distortion.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4717631 (1988-01-01), Kaganowicz et al.
patent: 5252515 (1993-10-01), Tsai et al.
patent: 5600165 (1997-02-01), Tsukamoto et al.
patent: 5639687 (1997-06-01), Roman et al.
patent: 6153541 (2000-11-01), Yao et al.
patent: 6221558 (2001-04-01), Yao et al.
patent: 6228760 (2001-05-01), Yu et al.
W. W. Lee et al., “Inorganic ARC for 0.18um and Sub-0.18um Multilevel Metal Interconnects,” Proccedings of the IEEE 1998 International Interconnect Technology Conference, Jun. 1998, pp. 84-86.
Wang Pin-Ting
Yao Liang-Gi
Ackerman Stephen B.
Bowers Charles
Saile George O.
Smoot Stephen W.
Stoffel William J.
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