Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-17
2002-01-22
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S524000
Reexamination Certificate
active
06340615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memories and, more particularly, to methods of connecting a storage capacitor plate to a pass transistor conducting terminal in dynamic random access memory cells.
2. Background Description
Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge coupled to a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. The absence or presence of charge on the capacitor corresponds to a logic value of data stored in the cell. Because cell size determines chip density, size and cost, reducing cell area is one of the DRAM designer's primary goals.
Reducing cell area is done, normally, by shrinking feature sizes to shrink the cell. In addition to shrinking the cell features, the most effective way to reduce cell area is to reduce the largest feature in the cell, typically, the area of the storage capacitor. Unfortunately, shrinking the capacitor area reduces capacitance and, consequently, reduces stored charge. Reduced charge means that what is stored in the DRAM cell is more susceptible to noise, soft errors, leakage and other well known DRAM problems.
Also, each cell is read by coupling the cell's storage capacitor (through the access transistor) to a bitline, which is a larger capacitance, and measuring the resulting voltage difference on the bit line. So, since the voltage difference is proportional to the two capacitances, reducing the cell storable capacitance reduces the voltage difference. Consequently, another DRAM cell designer's goal is to maintain storage capacitance, thereby maximizing stored charge without sacrificing cell area.
One way to reduce DRAM cell size without necessarily reducing storage capacitance is to use trench capacitors in the cells. Typically, trench capacitors are formed by etching long deep trenches in a silicon wafer, selectively doping the trench sidewalls, coating the trench with a dielectric layer. Then, the coated trench is filled with polysilicon or amorphous silicon to form a vertical cell capacitor plate and, as a result, a cell capacitor on its side in the trench. Thus, the silicon surface “real estate” required for the storage capacitor is dramatically reduced without sacrificing capacitance.
The typical bit line signal is a few hundred millivolts (mV) that develops asymptotically from the time that the access transistor is turned on as a function of the series resistance between the two capacitances. To achieve high performance, state of the art sense amplifiers must sense a voltage difference that is something less than the final signal value of a few hundred millivolts. Any resistance between the bitline and the storage capacitor of the cell being read increases the collective signal path RC and, as a result, increases the time required to develop a sufficient bit line signal, large enough to sense.
For state of the art trench capacitor DRAM cells, the plate is strapped to the access transistor's source diffusion, typically, with doped polysilicon or doped amorphous silicon. The doped strap forms a pn junction that acts as, or merges with the source diffusion junction. The strap, which may be buried beneath the chip surface and connects the deep trench capacitor to the access transistor, forms a resistive connection, ideally with very low resistance.
However, strap resistance may be high enough to cause concern for DRAM cell designers. The resistance of the strap itself, the resistance of the contacts between the strap and the plates or the resistance of the source diffusion, may be high enough to slow down cell read access beyond an acceptable range and, to a lesser extent, may also slow down writing to the cell. If all cells are affected, the read and write timing might be adjusted to compensate for the additional delay; if individual cells are affected, the affected cells will appear as individual failures. However, regardless of how the problem exhibits itself, high resistance straps reduce DRAM yield when too may cells fail or when overall access time becomes excessively long.
One known approach to reducing strap resistance is to implant dopant impurities at an angle to the trench sidewalls prior to forming the straps, thereby doping the area to which the buried strap is contacted. Implanting trench sidewalls at an angle requires rotating the wafers at least twice during implantation (180° rotations, one for each trench sidewall) to dope all buried strap contact areas appropriately. However, this two direction approach restricts the cell active area orientation, layout and design rules. Here, the active area refers to the silicon surface area on which the access transistor and bit line contact are located and isolated with shallow trench isolation. The orientation restrictions may be overcome by rotating the wafer four or more times with, for example, 90 degrees for each rotation. Unfortunately, to avoid affecting device active area adjacent to the trenches, ion implant energy and angle of implant must be limited for this four way rotation. Although these process changes help reduce buried strap resistance, they result in increased process complexity, raise chip cost and impede wafer throughput, besides restricting cell active area.
Thus there is a need for a simple way to form low resistance strap connections for trench capacitor DRAM cells.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to decrease the Dynamic Random Access Memory (DRAM) cell access;
It is another purpose of the present invention to reduce resistance in DRAM cell storage capacitance connections;
It is yet another purpose of the present invention to reduce DRAM cell access time by reducing trench capacitor plate connection resistance.
The present invention is a method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around trench openings. Then, the straps and trench sidewalls can be doped with a vertical implant to form a resistive connection reliably. Exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate during the subsequent STI processing.
REFERENCES:
patent: 5827765 (1998-10-01), Stengl et al.
patent: 5895255 (1999-04-01), Tsuchiaki
patent: 6211006 (2001-04-01), Tsai et al.
Divakaruni Rama
Ho Herbert L.
Iyer Subramanian
Iyer Sundar K.
Khan Babar A.
Chaudhari Chandra
Petraske Eric W.
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