Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-08-23
2011-08-23
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000, C714S718000, C714S721000, C714S025000, C714S030000, C714S036000, C365S201000
Reexamination Certificate
active
08006148
ABSTRACT:
A test mode control circuit of a semiconductor memory device includes an input unit configured to input test mode data for at least one of a plurality of test modes, and a test mode controlling unit configured to enable/disable a test mode according to the number of inputs of the test mode data.
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Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Sep. 29, 2009 with an English Translation.
Hynix / Semiconductor Inc.
IP & T Group LLP
Trimmings John P
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