Multiple independent coherence planes for maintaining coherency

Details Multiple independent coherence planes for maintaining coherency Multiple independent coherence planes for maintaining coherency

2008-04-01

2008-04-01

Lane, Jack (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S147000, C711S202000, C711S203000, C709S216000, C709S245000

Reexamination Certificate

active

07353340

ABSTRACT:
In one embodiment, a node comprises at least one processor core and a plurality of coherence units. The processor core is configured to generate an address to access a memory location. The address maps to a first coherence plane of a plurality of coherence planes. Coherence activity is performed within each coherence plane independent of other coherence planes, and a mapping of the address space to the coherence planes is independent of a physical location of the addressed memory in a distributed system memory. Each coherence unit corresponds to a respective coherence plane and is configured to manage coherency for the node and for the respective coherence plane. The coherence units operate independent of each other, and a first coherence unit corresponding to the first coherence plane is coupled to receive the address if external coherency activity is needed to complete the access to the memory location.

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