Methods of forming semiconductor devices with high-k gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21625

Reexamination Certificate

active

07354830

ABSTRACT:
A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

REFERENCES:
patent: 5321289 (1994-06-01), Baba et al.
patent: 5668035 (1997-09-01), Fang et al.
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6015739 (2000-01-01), Gardner et al.
patent: 6030862 (2000-02-01), Kepler
patent: 6166417 (2000-12-01), Bai et al.
patent: 6168958 (2001-01-01), Gardner et al.
patent: 6221114 (2001-04-01), Würthner et al.
patent: 6265325 (2001-07-01), Cao et al.
patent: 6303418 (2001-10-01), Cha et al.
patent: 6383861 (2002-05-01), Gonzalez et al.
patent: 6432776 (2002-08-01), Ono
patent: 6448127 (2002-09-01), Xiang et al.
patent: 6479341 (2002-11-01), Lu
patent: 6495422 (2002-12-01), Yu et al.
patent: 6528374 (2003-03-01), Bojarczuk, Jr. et al.
patent: 6528858 (2003-03-01), Yu et al.
patent: 6632714 (2003-10-01), Yoshikawa
patent: 6640403 (2003-11-01), Shih et al.
patent: 6737354 (2004-05-01), Miles et al.
patent: 6777761 (2004-08-01), Clevenger et al.
patent: 6906398 (2005-06-01), Yeo et al.
patent: 6927414 (2005-08-01), Ouyang et al.
patent: 7045847 (2006-05-01), Lin et al.
patent: 2004/0198009 (2004-10-01), Chen et al.
patent: 2005/0048722 (2005-03-01), Saito et al.
patent: 2006/0011949 (2006-01-01), Yang et al.
patent: 2006/0024893 (2006-02-01), Min et al.
patent: 2006/0211195 (2006-09-01), Luan
patent: 426941 (2001-03-01), None
“Bake and Cure of Low-k Dielectric Layers,” Koyo Thermo Systems Co., Ltd., http://www.crystec.com/killowe.htm. Jan. 7, 2004.
Chen, et al., “Downscaling Limit of Equivalent Oxide Thickness in Formation of Ultrathin Gate Dielectric by Thermal-Enhanced Remote Plasma Nitridation,” IEEE Transactions on Electron Devices, May 2002, vol. 49, No. 5, pp. 840-846.
Gustafsson, et al., “High-Resolution Depth Profiling Of Ultrathin Gate Oxides Using Medium-Energy Ion Scattering,” Nuclear Instruments And Methods In Physics Research B 183, 2001, pp. 146-153.
Mahapatra, et al., “ZrO2As A High-k Dielectric For Strained SiGe MOS Devices,” Bull. Mater. Sci., Nov. 2002, vol. 25, No. 6, pp. 455-457.
Yeo, et al., “Direct Tunneling Leakage Current And Scalability Of Alternative Gate Dielectrics,” Applied Physics Letters, Sep. 9, 2002, vol. 81, No. 11, pp. 2091-2093.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of forming semiconductor devices with high-k gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of forming semiconductor devices with high-k gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming semiconductor devices with high-k gate... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2779456

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.