High speed ATPG testing circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S727000, C714S734000, C714S735000

Reexamination Certificate

active

07900107

ABSTRACT:
The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.

REFERENCES:
patent: 5621739 (1997-04-01), Sine et al.
patent: 7263642 (2007-08-01), Makar et al.
patent: 7487412 (2009-02-01), Baeg et al.
patent: 2005/0055615 (2005-03-01), Agashe et al.
patent: 2005/0138501 (2005-06-01), Motika et al.
patent: 2006/0248419 (2006-11-01), Colunga et al.
patent: 2009/0132879 (2009-05-01), Gangappa

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