Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-01-04
2011-01-04
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S613000, C257SE51040
Reexamination Certificate
active
07863138
ABSTRACT:
A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.
REFERENCES:
patent: 6781166 (2004-08-01), Lieber et al.
patent: 2004/0228961 (2004-11-01), Smits et al.
patent: 2005/0189859 (2005-09-01), Tsuruoka et al.
patent: 2006/0141222 (2006-06-01), Fischer et al.
patent: 2007/0265379 (2007-11-01), Chen et al.
patent: 2008/0303029 (2008-12-01), Kawashima et al.
patent: 2005-169614 (2005-06-01), None
patent: 1020030032726 (2003-04-01), None
patent: 1020050060080 (2005-06-01), None
patent: 1020050116925 (2005-12-01), None
patent: 1020050121443 (2005-12-01), None
patent: 10-0593257 (2006-06-01), None
Sheu et al. “Preparation of nano-scale patterns on the silicon oxide surface by dip-pen nanolithography”,Nanotechnology, 5thIEEE Conference2:701-704 (2005).
Notice of Allowance corresponding to Korean Application No. 10-2006-0112875 mailed Feb. 21, 2008.
Office Action corresponding to Korean Application No. 10-2006-0112875 mailed Oct. 24, 2007.
Huo Zong-Liang
Mayya Subramanya
Wang Xiaofeng
Yeo In-Seok
Coleman W. David
Enad Christine
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
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