Critical path redundant logic for mitigation of hardware...

Details Critical path redundant logic for mitigation of hardware... Critical path redundant logic for mitigation of hardware...

2011-03-01

2011-03-01

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S009000, C326S014000

Reexamination Certificate

active

07898286

ABSTRACT:
Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.

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Andreas Veneris, et al.; “Design Rewiring Using ATPG”; IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, vol. 21, No. 12, Dec. 2002; pp. 1469-1479.

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