Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-08-21
2001-11-20
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189050, C365S189110, C365S201000, C365S225700
Reexamination Certificate
active
06320801
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, a semiconductor memory device having a redundancy circuit.
2. Description of the Related Invention
Modern graphic systems with enhanced resolution and three-dimensional capability often include RAMBUS™ DRAM (Dynamic Random Access Memory) or MMLs (Merged Memory Logic) to satisfy the memory requirements for effective graphic operation. RAMBUS DRAMs and MMLs have more data I/O (input and output) lines than column select lines to increase data I/O bits. These semiconductor memory devices have word lines and column select lines extending in the same direction and data I/O lines and bit lines extending perpendicular to the word lines.
The above-described semiconductor memory devices generally include redundant data I/O lines connected to redundancy memory cells for replacement of defective memory cells and associated data I/O lines. Using these redundancy circuits, a redundancy method can replace a defective bank, block, or column address group with a redundant bank, block, or column address group.
FIG.1
is a block diagram of a semiconductor memory device using a known bank redundancy method. The semiconductor memory device includes two memory cell array banks BANK
0
and BANK
1
, and each of the two memory cell array banks BANK
0
and BANK
1
contains four memory cell arrays BLA, BLB, BLC, and BLD. Each of the four memory cell arrays includes a normal block NB and a redundant block RB. In a bank redundancy method, if a partial block {circle around (
1
)} of array BLA of bank BANK
0
and a partial block {circle around (
2
)} of array BLA of bank BANK
1
are defective, partial blocks {circle around (
1
)} and {circle around (
2
)} and all partial blocks in corresponding locations of arrays BLB, BLC, BLD, are replaced with redundant blocks RB. Redundant blocks RB thus replace the partial blocks hatched on the left portions of arrays BLA, BLB, BLC, and BLD. Accordingly, a data I/O line IO
1
associated with the replaced blocks is replaced with a redundant data I/O line RIO.
If partial block {circle around (
2
)} of array BLA and a partial block {circle around (
3
)} of array BLB of bank BANK
1
are defective, one of the partial blocks {circle around (
2
)} and {circle around (
3
)} can be replaced with the redundant block RB, but the other partial block cannot be replaced with the redundant block RB. Accordingly, the bank redundancy method cannot repair this pattern of memory cell defects. That is, the bank redundancy method cannon repair the defective memory when two or more data il lines are associated with defective memory cells. A block redundancy method can repair the partial blocks {circle around (
2
)} and {circle around (
3
)}.
FIG. 2
is a block diagram of a semiconductor memory device using a known block redundancy method. The device has the same structure as the device of FIG.
1
. Referring to
FIG. 2
, when partial blocks {circle around (
1
)}′ and {circle around (
2
)}′ of arrays BLA and BLB of BANK
0
are defective, the block redundancy method replaces defective partial blocks {circle around (
1
)}′ and {circle around (
2
)}′ with redundant blocks RB of blocks BLA and BLB of bank BANK
0
. The method further replaces partial blocks (hatched in the same fashion as partial blocks {circle around (
1
)}′ and {circle around (
2
)}′)of bank BANK
1
, which are equivalently located to partial blocks {circle around (
1
)}′ and {circle around (
2
)}′ of bank BANK
0
, with redundant blocks RB of the memory cell arrays BLA and BLB of bank BANK
1
. In this method, redundant date I/O line RIO replaces data I/O line IO
1
or IO
4
depending on the array accessed.
When partial blocks {circle around (
1
)}′ and {circle around (
3
)}′ of array BLA of bank BANKO are defective, only one of partial blocks {circle around (
1
)}′ of the memory cell array block BLA can be replaced with the redundant partial block RB of array BLA. That is, the block redundancy method cannot repair multiple defective partial blocks in the same memory cell array.
FIG. 3
is a block diagram of a semiconductor memory device using a known column address group redundancy method. The device has the same structure as the device of FIG except that each partial block (including redundant partial block RB) includes four portions distinguished by column address group.
When defective portions {circle around (
1
)}″ and {circle around (
2
)}″ of array BLA of bank BANK
0
are in different column address groups, the column address group redundancy method replaces defective portions {circle around (
1
)}″ and {circle around (
2
)}″ of bank BANK
0
(and all portions of banks BANK
0
and BANK
1
in the same columns as portions {circle around (
1
)}″ and {circle around (
2
)}″) with the portions of redundant partial blocks RB that are respectively associated with the same column address group as portions {circle around (
1
)}″ and {circle around (
2
)}″. In
FIG. 3
, the crosshatched portions replace the hatched portions in respective arrays BLA, BLB, BLC, and BLD. Here, redundant data I/O line RIO replaces data I/O lines I
01
and I
04
when accessing columns corresponding to portions {circle around (
1
)}″ and {circle around (
2
)}″.
However, when portions {circle around (
1
)}″ and {circle around (
3
)}″, which are associated to the same column address group, are defective, the column address group redundancy method can replace only one of portions {circle around (
1
)}″ and {circle around (
3
)}″ with the corresponding portion of redundant partial block RB. That is, the column address group redundancy method cannot repair this kind of defect pattern.
Semiconductor memory devices usually select one of the three redundancy methods described above and thus cannot repair all kinds of defective memory cell patterns.
SUMMARY OF THE INVENTION
An embodiment of the present invention is a redundancy circuit of a semiconductor memory device. The redundancy circuit includes: a mode setting circuit that generates mode signals, which respectively correspond to redundancy modes; an input selecting circuit that generates mode selecting signals in response to the mode signals; and a decoding circuit that, in response to the mode selecting signals, generates decoding signals that initiate a replacement of a data I/O line pair associated with a defective memory cell in the semiconductor memory device.
One embodiment of the decoding circuit includes: a defective address setting circuit that receives the mode selecting signals and generates a redundancy operation control signal and data I/O line pair address signals; a predecoder that receives the redundancy operation control signal and the address signals and generates pre-decoding signals; and decoders that decode the pre-decoding signals and generate decoding signals.
The mode signals include a bank redundancy mode signal, a block redundancy mode signal, and a column address group redundancy mode signal. The mode selecting signals include a bank selecting signal, a block selecting signal, and a column address group selecting signal.
Another embodiment of the present invention is a redundancy method for a semiconductor memory device that includes a mode setting circuit, an input selecting circuit, and a decoding circuit. The method includes: generating, in the mode setting circuit, redundancy mode signals, which respectively correspond to redundancy modes; generating, in the input selecting circuit, mode selecting signals in response to the redundancy mode signals; and generating, in the decoding circuit, decoding signals that initiate a replacement of a data I/O line pair associated to a defective memory cell, in response to the mode selecting signals.
In one embodiment of the method, the decoding signals indicate the location of the defective data I/O line pair, so that the defective data I/O line pair is re
Dinh Son T.
Heid David W.
Samsung Electronics Co,. Ltd.
Skyjerven Morrill MacPherson LLP
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