Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-09-29
2001-10-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06308293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fault diagnosis apparatus for an LSI, and more particularly to a fault diagnosis apparatus useful for a disconnection fault of a wiring pattern and a recording medium on which a fault diagnosis program is recorded.
2. Description of the Related Art
As a technique useful for a fault diagnosis of an LSI, a method is available which employs an apparatus which can directly observe a signal behavior in the inside of an LSI (an apparatus of the type mentioned is hereinafter referred to an internal signal observation apparatus) such as electron beam tester (EB tester). However, since an internal signal observation apparatus of the type described requires much time for measurement, it is not effective for a large scale circuit to use only the internal signal observation apparatus from the beginning to trace or search for a fault site from an output with which an error has been observed since a very long time is required for observation of signals and narrowing down of fault site candidates.
Thus, several fault diagnosis techniques have been proposed wherein fault sites in an LSI are estimated from a result of comparison between output signals and scan-out signals of the LSI obtained from an LSI tester and expected values for them and places to be observed directly are reduced by a large number by means of an internal signal observation apparatus such as an EB tester.
For example, Japanese Patent Laid-Open Application No. Heisei 1-244384 discloses a technique wherein a circuit pattern in which only one route is activated from an input to an output of the circuit is used to perform a test and a fault site is estimated from failed outputs and passed outputs by comparison with expected values obtained by an LSI tester and a list of faults which are activated with the pattern then (hereinafter referred to as first prior art).
Japanese Patent Laid-Open Application No. Heisei 4-55776 discloses another technique which compares, making use of a fact that a designer can estimate a gate or a state which makes a cause of a fault from a result of a test by an LSI tester, a result of a simulation performed by assuming suspected fault sites and a result of comparison with expected values by an LSI tester to verify whether or not the estimation is correct (hereinafter referred to as second prior art).
Among various faults of LSI circuits, a disconnection of a wiring pattern and a disconnection by an incomplete contact exhibit high frequencies of occurrence. For example, a disconnection of a wiring line pattern upon production of an LSI which is caused by dust on a mask, a disconnection which arises from flowing of overcurrent during operation and a disconnection which is caused by deterioration by use for a long period of time are possible. Most wiring patterns have branches, and if a disconnection occurs intermediately of a branch, then a signal operates normally at a portion of the branch forwardly of the disconnected site while the signal does not operate in the branch rearwardly of the disconnected site but is fixed, entering a fault mode which cannot be represented by a single stuck-at fault.
The first prior art described above has a problem in that, since it presumes a single stuck-at fault as a fault, for such a disconnection fault of a wiring pattern which is a fault mode which cannot be represented by a single stuck-at fault as described above, it cannot effectively narrow down fault site candidates.
On the other hand, the second prior art can handle any fault and can diagnose also a disconnection fault intermediate of a branch of a wiring line. However, as an increase in scale and complication of a circuit proceeds, an increasing number of designers participate in cooperative development of an LSI, resulting in such a situation that almost none of the designers possibly knows the entire circuitry of the LSI to such a degree that a possible fault site can be estimated. Accordingly, the second prior art which presumes that a possible fault can be estimated by a designer cannot be applied well to an LSI of a large scale. Further, even if the second prior art is applied, if a designer estimates fault sites and confirms them one after another by a simulation, then very much labor is required, and therefore, this is not practical.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a fault diagnosis apparatus which can narrow down, for a disconnection fault intermediate of a branch wiring line which cannot conventionally be diagnosed automatically, fault site candidates with a high degree of accuracy based on a result of comparison with expected values by means of an LSI tester.
In order to attain the object described above, according to the present invention, an error test pattern which is a test pattern with which outputs of expected values have not been obtained by an LSI test for a fault diagnosis object LSI or the like is utilized to perform narrowing down of fault candidates based on a condition to be satisfied where the LSI suffers from a disconnection fault intermediate of a branch wiring line.
More particularly, according to an aspect of the present invention, there is provided a fault diagnosis apparatus which estimates a fault site in a fault diagnosis object LSI based on a result of an LSI test performed using a test pattern for the LSI, comprising suspected fault gate setting means for setting candidates for a suspected fault gate to a suspected fault gate set, and output value check narrowing down means for checking, for each of the suspected fault gates included in the suspected fault gate set, whether or not a condition is satisfied that an output value of the suspected fault gate at least in an error test pattern is different from that of the suspected fault gate in the other error test patterns, and removing those of the suspected fault gates with which the condition is satisfied from the suspected fault gate set.
The fault diagnosis apparatus may comprise, in place of or in addition to the output value check narrowing down means, branch destination fault simulation narrowing down means for defining a 1/0 stuck-at fault to each of output branch destinations of the suspected fault gates included in the suspected fault gate set and performing a fault simulation for each one test pattern, removing, for each fault simulation, the fault definitions of output branch destinations detected with normal outputs, and removing those of the suspected fault gates from which the fault definitions of all of the respective output branch destinations have been removed and those of the suspected fault gates with which, in any of the error test patterns, none of the fault definitions of the respective output branch destinations have not been detected with outputs which are determined to be errors with the error test pattern from the suspected fault gate set.
The fault diagnosis apparatus may further comprise indefinite value simulation narrowing down means for performing, for each of the suspected fault gates included in the suspected fault gate set, a simulation in which an error test pattern is used and an output of the suspected fault gate is set to an indefinite value and removing any of the suspected fault gates with which at least one of those outputs which have been determined to be errors with the error test pattern exhibits a definite value from the suspected fault gate set.
While the plurality of narrowing down means may be applied in any order, since the indefinite value simulation narrowing down means can be constructed so as to operate at a higher speed than the other narrowing down means, the fault diagnosis apparatus is preferably constructed such that, for the suspected fault gate set after narrowing down of candidates for the suspected fault gate by the indefinite value simulation narrowing down means is performed, narrowing down of the candidates for the suspected fault gate by the output value check narrowing down means or by the branch destination fault simulation narrowin
De'cady Albert
Foley & Lardner
Lamarre Guy
NEC Corporation
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