Method for fabricating a high-density semiconductor memory...

Details Method for fabricating a high-density semiconductor memory... Method for fabricating a high-density semiconductor memory...

1999-02-22

2001-10-02

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S459000, C438S977000

Reexamination Certificate

active

06297090

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods for fabricating high-density semiconductor memory devices, and more particularly, to methods for fabricating high-density dynamic random access memories (DRAMs) utilizing an SOI (silicon on insulator) technique by bonding two bulk silicon wafers.
BACKGROUND OF THE INVENTION
Bit density of semiconductor memories increases four times per three years and operation speeds thereof also increase. Such development in semiconductor memories enables 1 GHz (giga hertz) operation speed for a 1 Gb (giga bit) DRAM (dynamic random access memory) device.
In DRAM devices, an 8F
2
memory cell size adopted in a 64K DRAM density era has been employed up to now. The 8F
2
memory cell is called as a folded bit line cell architecture in view of bit line arrangement with respect to a sense amplifier. The 8F
2
is the smallest theoretical cell size of the folded bit line cell architecture. Herein, the F depicts a minimum feature size and is normally determined by a minimum design rule which can be patterned. The F may also mean half(½) of parallel bit line pitch comprising a memory cell array. For example, a smallest cell size of a 0.6 &mgr;m pitch becomes 8×0.3×0.3=0.72 &mgr;m
2
.
FIG. 1A
shows a layout of a memory cell having an 8F
2
folded bit line cell architecture of a COB (capacitor over bit line) that is mainly used in the present high-density DRAM.
FIG. 1B
is a cross-sectional view taken along a line
1
A-
1
A′ of FIG.
1
A.
Referring to FIG.
1
A and
FIG. 1B
, a transistor
6
having a gate electrode (word line (WL)) and source and drain regions (not shown) is formed on a semiconductor substrate
1
where a device isolation layer
2
is formed. Contact pads are formed to be electrically connected to an active region
3
between the word lines. The contact pads include a storage electrode contact pad
8
a
and a bit line contact pad
8
b
. A storage electrode
16
and a bit line
11
are formed to be respectively connected with the storage electrode contact pad
8
a
and the bit line contact pad
8
b
through selected interlayer insulating films
10
,
12
. Herein, the bit line
11
is formed under the storage electrode
16
, i.e., the bit line
11
is formed before the formation of the storage electrode
16
.
In foregoing COB memory cell architectures, since a memory cell capacitor is formed after formation of the word line (WL) and bit line
11
, a memory cell contact hole
14
has an inevitably high aspect ratio. In other words, the interlayer insulating film
12
is thick and it is difficult to open a contact hole therein. To solve the problem of etching the high aspect ratio contact hole
14
, a process of forming a landing pad, so called cell pad, is generally used.
It is impossible, however, to form a silicide layer simultaneously on a top surface of a gate and a source/drain in the landing pad application. As a result, it becomes complex and difficult to implement a high performance logic device and DRAM device together. In addition, the misalignment of word line or bit line may cause shorts between a memory cell and a word line, or between a memory cell and a bit line, during the step of forming memory cell contact. These inherent problems stand in the way of reduction of DRAM cell density and implementation of a large capacity and high performance DRAM cell.
Once the minimum feature size (F) is decided, a minimum cell size is decided and an area occupied by an array according to DRAM density is calculated. The area occupied by array is given as ‘Nbit×cell size’. In case of a 1 Gb DRAM, for example, the Nbit corresponds to 2
30
(=1,073,741,824). The ratio of the array area with respect to a total chip size is called as ‘array efficiency’. The array efficiency, in case of high-density DRAM devices, such as a 64 Mb DRAM and more, is about 65%. Accordingly, the chip size is expressed by a following equation as a function of minimum feature size (F).
S
C
=&agr;
−1
×N
bit
×8F
2
Herein, S
C
denotes a chip size and &agr; denotes an array efficiency. The calculation of a DRAM chip size according to a minimum feature size or density in accordance with foregoing equation is shown in FIG.
2
. Herein, the chip size is calculated in accordance with an 8F
2
folded bit line cell architecture and array efficiency of 65% in every memory device density era.
In
FIG. 2
, it is expected that a 1 Gb chip size will be about 425 mm
2
, 4 Gb about 960 mm
2
, and 16 Gb about 2000 mm
2
. It is expected to be very difficult to obtain a good chip yield from such a large chip size and it is well known that the yield is in inverse proportion to a chip size. For a cost-effective high-density DRAM, therefore, it is a necessary that a memory cell size be made from the same minimum feature size. It is well known in the art that the minimum cell size of an open line cell architecture is 6F
2
(remember that 8F
2
is the minimum cell size of the folded bit line cell structure). The open bit line cell architecture is disadvantageous, however, because of its inferior noise immunity and because of difficulty in the sense amplifier layout.
A combined approach of open bit line layout and folded bit line sensing has also been recently reported. This approach is also disadvantageous, however, as it requires an additional mask.
SUMMARY OF THE INVENTION
The present invention was made in view of the above problem, and it is therefore an object of the invention to provide a high-density semiconductor memory device and a method thereof which can reduce a device isolation region, provide larger active region and thus advantageously reduce device dimension. The present invention utilizes bonded wafer, i.e., SOI substrate where memory device is built. The memory device is so fabricated on the bonded wafer that the areas required to isolate between well-to-well can be reduced, the size of the isolation space can also be reduced and thereby reducing chip size.
To achieve this and other advantages and in accordance with the purpose of the present invention, there are provided two wafers, i.e., process wafer and handle wafer. First, a trench etching mask is formed over the process wafer to define an active region and an inactive region. The exposed process wafer is then etched to form a trench. An insulating material is deposited in the trench and over the trench etching mask. Planarization process is carried out down to a top surface of the trench etching mask and thereby forming trench isolation. The trench isolation surrounds the active region to electrically isolate each active region. Selected portions of the trench etching mask is etched down to the active region of the process wafer to form a contact hole for a capacitor lower electrode. A conductive material is deposited in the contact hole and over the trench etching mask and the trench isolation and then patterned to form a lower electrode. A dielectric film and an upper electrode are deposited to form a capacitor. The upper electrode is planarized. The planarized upper electrode of the process wafer and the handle wafer are bonded together disposing a bonding insulating layer therebetween. The surface of the process wafer of the bonded wafer is planarized down to a top surface of the trench isolation. A transistor is formed over the planarized surface of the process wafer of the banded wafer. The transistor includes a gate electrode and a junction region. An interlayer insulating layer is formed over the transistor to cover thereof The selected interlayer insulating layer is etched to form a bit line contact hole exposing the junction region. A conductive material is deposited in the bit line contact hole and over the interlayer insulating layer and patterned to form a bit line.
In aspect of the present invention, since the formation of the capacitor is followed by the formation of the transistor, the degradation of the transistor can be suppressed. The trench etching mask is not removed. Instead, the trench etching mask serves to sur

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