Semiconductor memory device having structure for high-speed...

Details Semiconductor memory device having structure for high-speed... Semiconductor memory device having structure for high-speed...

2000-07-10

2001-10-30

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189011

Reexamination Certificate

active

06310808

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to the structures of a data input/output gate and a write driver.
2. Description of the Prior Art
A system LSI (large scale integrated circuit) having a memory core part (synchronous semiconductor memory device) and a logic circuit controlling the memory core part on the same substrate is developed. The memory core part includes hundreds of data input/output terminals (DQ terminals), for improving the data transfer rate between the same and the logic circuit.
A principal part of such a conventional memory core part is described with reference to FIG.
24
. Referring to
FIG. 24
, symbol MC denotes memory cells, symbols WL
0
to WL
2
denote word lines, and each of symbols BL(
0
:n) and /BL(
0
:n) denotes a plurality of bit lines respectively. Symbols DQ(
0
), DQ(
1
), . . . , DQ(
7
) denote data input/output terminals for inputting/outputting data (or input/output data), and symbols GIO(
0
), /GIO(
0
), GIO(
1
), /GIO(
1
), . . . , GIO(
7
), /GIO(
7
) denote data input/output lines.
A row decoder
914
outputs a word line activation signal for selecting any word line of a memory cell array MA. Another row decoder
915
outputs another word line activation signal for selecting any word line of a memory cell array MB. When either word line activation signal is activated, data is read on any bit line from any memory cell MC or written in any memory cell MC from any bit line. A row decoder (SA)/column decoder
916
outputs a signal for controlling an S/A zone
930
.
A GIO line write driver/read amplifier zone
904
includes GIO line write drivers/read amplifiers
910
A,
910
B, . . . ,
910
H. Each of the GIO line write drivers/read amplifiers
910
A,
910
B, . . . ,
910
H is arranged for each of the data input/output terminals DQ(
0
) to DQ(
7
).
The S/A zone
930
includes SA/input/output circuit blocks
902
A,
902
B, . . . ,
902
H. Each of the SA/input/output circuit blocks
902
A,
902
B, . . . ,
902
H includes a plurality of sets of sense amplifiers and input/output circuits.
A write mask signal WM is input when no data is rewritten in only a certain bit in a write operation. The 1-bit write mask signal WM controls the 8-bit data input/output lines GIO(
0
), /GIO(
0
), . . . GIO(
7
), /GIO(
7
).
The structure of each SA/input/output circuit block is described with reference to FIG.
25
.
FIG. 25
shows the S/A input/output circuit block
902
A, for example. The SA/input/output circuit block
902
A includes a plurality of blocks SAX
0
, . . . , SAXn. Each of the blocks SAX
0
, . . . , SAXn includes a sense amplifier SA, an equalization circuit EQ and NMOS transistors TLa, TLb, TRa and TRb.
The sense amplifier SA is activated in response to sense amplifier activation signals SE and /SE. The sense amplifier SA includes a cross-coupled latch amplifying read data read from any memory cell and a circuit transferring write data to any bit line. The equalization circuit EQ equalizes any pair of bit lines in response to a bit line equalization signal BLEQ.
A gate formed by the transistors TLa and TLb is turned on by a signal SHRL for connecting the SA/input/output circuit block
902
A with the memory cell array MA. A gate formed by the transistors TRa and TRb is turned on by a signal SHRR for connecting the SA/input/output block
902
A with the memory cell array MB. The two memory cell arrays MA and MB share the sense amplifier SA through these gates.
Each of the blocks SAX
0
, . . . , SAXn further includes an input/output circuit controlled by a column selection signal CSL. For example, the block SAX
0
includes an input/output circuit formed by NMOS transistors Q
0
and /Q
0
, and the block SAXn includes an input/output circuit formed by NMOS transistors Qn and /Qn.
The transistors Q
0
and /Q
0
receive a column selection signal CSL(
0
) in the gates thereof while the transistors Qn and /Qn receive a column selection signal CSL(n) in the gates thereof.
In a read operation, one of n sense amplifiers SA is selected by the column selection signals CSL(
0
) to CSL(n). Selected read data is transferred to any pair of data input/output lines. In the write operation, write data is transferred from a sense amplifier selected by the column selection signals CSL(
0
) to CSL(n) to any bit line. Thus, the data is written in any memory cell.
The structure of each GIO line write driver/read amplifier is now described with reference to FIG.
26
. The GIO line write driver/read amplifier
910
shown in
FIG. 26
includes a GIO line write driver
950
for the write operation, a read amplifier
952
for the read operation and a GIO line equalization circuit
954
.
The GIO line write driver
950
includes inverters IV
91
to IV
95
, NAND circuits NA
91
and NA
92
, NMOS transistors T
92
and T
94
and PMOS transistors T
91
and T
93
.
The NAND circuit NA
91
receives write data WD and a write mask signal /WM obtained by inverting the write mask signal WM in the inputs thereof, and the NAND circuit NA
92
receives output of the inverter IV
91
inverting the write data WD and the write mask signal /WM in the inputs thereof. The inverter IV
92
inverts the output of the NAND circuit NA
91
, and the inverter IV
93
inverts the output of the inverter IV
92
. The inverter IV
94
inverts the output of the NAND circuit NA
92
, and the inverter IV
95
inverts the output of the inverter IV
94
.
The transistors T
91
and T
92
are connected between a node receiving a power supply voltage Vcc and a node receiving a ground voltage. The transistors T
93
and T
94
are connected between a node receiving the power supply voltage Vcc and a node receiving the ground voltage. The gates of the transistors T
91
and T
92
receive the outputs of the inverter IV
93
and IV
92
respectively, and the gates of the transistors T
93
and T
94
receive the outputs of the inverter IV
95
and IV
92
respectively. The data input/output line GIO is connected with the node between the transistors T
91
and T
92
, and the data input/output line /GIO is connected with the node between the transistors T
93
and T
94
.
The GIO line equalization circuit
954
includes PMOS transistors T
95
, T
96
and T
97
receiving a signal GIOEQ in the gates thereof. The transistor T
95
is connected between the data input/output lines GIO and /GIO. The transistor T
96
is connected between the data input/output line GIO and a node receiving the power supply voltage Vcc, and the transistor T
97
is connected between the node receiving the power supply voltage Vcc and the data input/output line /GIO. The pair of data input/output lines GIO and /GIO are equalized in response to the signal GIOEQ.
The read amplifier
952
differentially amplifies data of the pair of data input/output lines GIO and /GIO and outputs read data RD.
In the write operation, the write mask signal /WM is set high. When the write data WD is high, the data input/output line GIO goes high and the data input/output line /GIO goes low. When the write data WD is low, the data input/output line GIO goes low and the data input/output line /GIO goes high.
In the read operation, the write mask signal /WM is set low for bringing the GIO line write driver
950
into a floating state. Read data of a bit line selected by the column selection signal CSL is transferred to the pair of data input/output lines GIO and /GIO. The read amplifier
952
amplifies complementary data received from the pair of data input/output lines GIO and /GIO. Thereafter the GIO line equalization circuit
954
precharges the pair of data input/output lines GIO and /GIO high, to prepare for reading next data.
The write operation/read operation in the conventional semiconductor memory device is described with reference to FIG.
27
. At a time t1, the signal GIOEQ and the write mask signal /WM go high. The write data WD is transferred to the pair of data input/output lines GIO and /GIO. The write data WD is high and hence the data input/output line /GIO goes low.
The

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