Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-29
2001-02-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S515000
Reexamination Certificate
active
06187643
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor device manufacturing and, more particularly, to the use of low energy, high tilt angle and high energy post-gate ion implantation (PoGI) to simplify semiconductor device manufacturing.
BACKGROUND OF THE INVENTION
Complementary metal oxide semiconductor (CMOS) technology has come into standard use in semiconductor device manufacturing. CMOS circuits include combinations of p-type MOS devices and n-type MOS devices, and are characterized by low power consumption and high packaging density. A significant trend in semiconductor device manufacturing is toward reduced device dimensions, resulting in increased packaging density and increased circuit complexity. As device dimensions are reduced, processes become more complex. Notwithstanding the increased complexity, processing costs must be carefully controlled.
A current front end of line (FEOL) CMOS process typically involves the use of eight patterned masks, six of which are implant masks. First and second implant masks are used to dope the substrate surface by n-type and p-type ion implantation prior to formation of gate electrodes. These doped regions are called n-wells and and p-wells, and can contain multiple dopant profiles, such as wells, channel stops, punch through stops and threshold adjusts. After formation of gate electrodes, a third implant mask is used for a p+ source/drain extension implant and an optional halo implant, and a fourth implant mask is used for an n+ source/drain extension implant and an optional halo implant. After deposition and etching of a sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes, a fifth implant mask is used for a p+ source/drain implant, and a sixth implant mask is used for an n+ source/drain implant. It is estimated that each mask adds approximately 30 dollars to the cost of an eight inch semiconductor wafer. In addition, multiple implant masks increase processing time and increase the risk of processing error.
A CMOS process utilizing post gate implantation of wells, channels and source/drains is disclosed by H. Mikoshiba et al in “A Novel CMOS Process Utilizing After-Gate-Implantation Process”, IEEE, 1986 Symposium on VLSI Technology, June 1986, pages 41-42.
A technique for forming super-steep retrograde channel profiles using ion implantation through the gate is disclosed by Y. V. Ponomarev et al in “Channel Profile Engineering of 0.1 &mgr;m-Si MOSFET's by Through-the-Gate Implantation”, IEEE, IEDM-98, Dec. 1998, pages 635-638.
A shallow junction well FET structure, wherein ion implantations for a shallow p-well and n-well were performed through the gate electrodes, is disclosed by H. Yoshimura et al in “New CMOS Shallow Junction Well FET Structure (CMOS-SJET) For Low Power-Supply Voltage”, IEEE, IEDM-92, Dec. 1992, pages 35.8.1-35.8.4.
A CMOS fabrication process wherein CMOS vertically modulated wells are constructed by using clustered MeV ion implantation to form a structure having a buried implanted layer for lateral isolation is disclosed in U.S. Pat. No. 5,501,993 issued Mar. 26, 1996 to Borland; U.S. Pat. No. 5,814,866 issued Sep. 29, 1998 to Borland; and U.S. Pat. No. 5,821,589 issued Oct. 13, 1998 to Borland.
All of the known prior art semiconductor fabrication processes have one or more disadvantages, including a high degree of complexity and high cost. Accordingly, there is a need for simplified semiconductor fabrication processes which are capable of producing high density devices at low cost.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method is provided for use in the fabrication of a circuit on a substrate. After formation of gate electrodes, a sidewall insulator layer is deposited on the substrate, and the sidewall insulator layer is etched to form sidewall spacers on the sides of the gate electrodes. Source/drain extensions and source/drain regions of p-type devices are implanted through openings in a first mask. Source/drain extensions and source/drain regions of n-type devices are implanted through openings in a second mask. The steps of implanting source/drain extensions are performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, so that the source/drain extensions are formed laterally under the sidewall spacers. The source/drain extensions optionally may be formed under portions of the gate electrodes. The steps of implanting the source/drain regions are performed at low or zero tilt angle with respect to a normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting the source/drain extensions.
An optional halo or pocket implant through the openings in the first mask may be used to form n-type pocket implants in the p-type devices. An optional halo or pocket implant through the openings in the second mask may be used to form p-type pocket implants in the n-type devices.
According to a feature of the invention, the method may further comprise implanting an n-well, a channel stop, and a threshold adjust for the p-type devices through the openings in the first mask. An optional punchthrough stop for the p-type devices may be implanted through the openings in the first mask. The steps of implanting the n-well, the channel stop and the threshold adjust for the p-type devices are performed at sufficient energy to pass through the gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface. The method may further comprise implanting a p-well, a channel stop, and a threshold adjust for the n-type devices through the openings in the second mask. An optional punchthrough stop for the n-type devices may be implanted through the openings in the second mask. The steps of implanting the p-well, the channel stop and the threshold adjust layer for the n-type devices are performed at sufficient energy to pass through the gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.
According to another feature of the invention, the method may further comprise the step of implanting a material, such as silicon or germanium, to form a pre-amorphorization layer prior to the steps of implanting source/drain extensions and implanting source/drain regions. Implantation of the pre-amorphorization layer facilitates a subsequent low temperature solid phase epitaxial regrowth step for low temperature dopant activation with minimal thermal diffusion.
According to a further feature of the invention, a p-well, a channel stop, and a threshold adjust for the n-type devices are implanted through non-open areas of a third mask prior to the step of forming the gate electrodes, and an n-well, a channel stop, and a threshold adjust for the p-type devices are implanted through openings in the third mask prior to the step of forming the gate electrodes.
According to another aspect of the invention, a method is provided for use in the fabrication of a device on a substrate. After formation of a gate electrode of the device, a sidewall insulator layer is deposited, and the sidewall insulator layer is etched to form sidewall spacers on the sides of the gate electrode. Source/drain extensions of the device are implanted through openings in a mask. The step of implanting source/drain extensions is performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein the source/drain extensions are formed laterally under the sidewall spacers. Source/drain regions of the device are implanted through the openings in the same mask. The step of implanting source/drain regions is performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the step of implanting source/drain extensions.
REFERENCES:
patent: 5501993 (1996-03-01), Borland
patent: 5571745 (1996-11-01), Horiuchi
patent: 5814866 (1998-09-01), Borland
patent: 5821589 (1998-10-01), Borland
patent: 5827747 (1998-10-01), W
Le Dung A
Nelms David
Varian Semiconductor Equipment Associates Inc.
Wolf Greenfield & Sacks P.C.
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