Method of fabricating dual damascene

Details Method of fabricating dual damascene Method of fabricating dual damascene

1999-10-12

2001-11-20

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S638000

Reexamination Certificate

active

06319814

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for a semiconductor. More particularly, the present invention relates to a method for fabricating a dual damascene.
2. Description of Related Art
As integration for integrated circuits (IC) increases, an interconnect design with more than two layers has gradually become the method of choice in many IC processes. An inter-metal dielectric (IMD) layer is often used to isolate between metal layers, while a conducting wire, which connects the top metal layer and the bottom metal layer, is known as a via in the semiconductor industry. The dual damascene process is a technology which involves simultaneously forming the via and the interconnect.
Conventionally, the IMD layer of the dual damascene is made of silicon oxide (SiO
x
) with a dielectric constant of about 4. To satisfy the need for fast development of the semiconductor industry, where RC delay is reduced to improve the data transfer rate, fluorinated silicon glass (FSG) with a lower dielectric constant (about 3.5) is currently used to replace silicon oxide as a material for forming the IMD layer.
FSG not only reduces the capacitance between interconnects, but is also compatible with the copper interconnect process. A silicon oxy-nitride layer or a silicon nitride layer, which would serve as an etching stop layer and copper diffusion barrier layer, respectively, is usually formed before formation of a FSG layer in the dual damascene process. As a result, a problem such as surface sensitivity, otherwise known as surface dependency, occurs when the FSG layer is formed on the silicon oxy-nitride layer or the silicon nitride layer, and has a serious effect on the subsequent semiconductor process.
FIG. 1
is a schematic, cross-sectional diagram illustrating a conventional process for fabricating dual damascene. First of all, a silicon nitride layer or silicon oxy-nitride layer
101
and a planarized fluorinated silicon glass (FSG) layer
102
are formed in sequence on a substrate
100
. A silicon nitride layer or silicon oxy-nitride layer
104
which serves as an etching stop layer and/or diffusion barrier layer is formed on the FSG layer
102
, wherein the silicon nitride layer or silicon oxy-nitride layer
104
has an opening. Another FSG layer
106
is then formed on the silicon nitride layer or silicon oxy-nitride layer
104
. In order to form a trench
108
and a via opening
110
which expose a conducting layer (not shown), the FSG layers
102
and
106
are etched respectively according to the required pattern of the metal conducting wire. So, an opening constituted of the trench
108
and via opening
110
is formed in the presence of the etching stop layer
104
. The trench
108
and the via opening
110
are then filled with a conducting layer
109
. Hence, the dual damascene process is the process which forms both the trench
108
and the via opening
110
as described.
However, FSG may not have a uniform deposition thickness on the chip surface and there may be a problem of surface sensitivity when the FSG layer is deposited on the silicon nitride layer or silicon oxy-nitride etching stop layer. As the FSG layer does not have a uniform thickness, the subsequent semiconductor process is affected.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a dual damascene, which method involves providing a substrate with a conducting layer formed within, wherein the conducting layer and the substrate have the same surface levels. A first undoped silicon glass (USG) liner is formed on the conducting layer and the dielectric layer followed by forming a FSG layer on the first USG liner. A stop layer which has an opening for exposing a part of the first FSG layer is formed on the first FSG layer, wherein the opening is located above the conducting layer. A second USG liner is formed to cover the stop layer and to fill the opening before forming a second FSG layer on the second USG liner. With the stop layer serving as an etching stop layer, the second FSG layer and the second USG liner are patterned to form a trench which exposes a part of the first FSG layer. The first FSG layer and the first USG liner are etched to form a via opening which exposes a part of the conducting layer. The first and the second USG liners have a thickness of about 100-500 angstroms.
As embodied and broadly described herein, the invention provides a method for fabricating an IMD layer, where a USG liner is formed on a substrate. A FSG layer is then formed on the USG liner, wherein the USG liner has a thickness of about 100-500 angstroms.
According to the present invention, a method applicable to the silicon nitride/silicon oxy-nitride layer on the substrate is provided for changing the surface condition. The method involves forming an USG liner on the silicon nitride/silicon oxy-nitride layer, followed by forming a FSG layer on the USG liner, wherein the USG liner has a thickness of about 100-500 angstroms.
In the present invention, a USG liner is formed before formation of the FSG layer, so that the surface condition between the silicon nitride/silicon oxy-nitride layer and the FSG layer is changed, while the surface dependence between the silicon nitride/silicon oxy-nitride layer and the FSG layer is eliminated. As a result, the thickness uniformity of the FSG layer is improved.
Furthermore, the USG liner also improves the adhesion between the FSG layer and other material layers.
According to the present invention, the USG liner is formed before deposition of the FSG layer. Experimental findings show that the problem of occurring particles on the chip is reduced during the fabrication process. Also, the USG liner disclosed in the invention changes the surface condition between the silicon nitride/silicon oxy-nitride layer and the FSG layer to make the subsequent FSG deposition easier. Although the USG liner has a dielectric constant approximately higher than that of the FSG layer, the USG liner with small thickness does not have a great impact on the effective dielectric constant of the whole integrated IMD layer. Also, the USG liner can improve the stability of the FSG layer in the following thermal cycle.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5937323 (1999-08-01), Orczyk et al.
patent: 5968610 (1999-10-01), Liu et al.
patent: 6153528 (2000-11-01), Lan
patent: 6184159 (2001-02-01), Lou et al.
patent: 5-226480 (1993-09-01), None

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