Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-16
2001-10-09
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S516000, C438S530000
Reexamination Certificate
active
06300208
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed to a method for annealing the source and drain regions of an integrated transistor device. More specifically, the invention can be used to melt and recrystallize the source and drain regions of an integrated transistor device to activate the junction thereof for proper electrical performance.
2. Description of the Related Art
As scaling of integrated devices progresses to below one-tenth of a micrometer (0.1 &mgr;m) with gate oxide thicknesses below thirty Angstroms (30 Å), severe problems are created by depletion of polysilicon gates, gate resistance and gate leakage. These problems have generated renewed interest in the use of metals for gates and alternative oxides for use as gate dielectric layers in processes for forming integrated devices. However, the use of metals for the gate electrode poses serious problems. Many processes for forming integrated devices involve a high-temperature anneal step in which the substrate is heated, often for extended periods of time, to activate the source and drain regions. This sort of extended thermal treatment is extremely destructive to most types of metals or dielectric stacks (i.e., multilayer structures that include conductive and dielectric layers) used for gate electrodes. Present proposals to overcome this problem add significant complexity to the process for forming an integrated device. It would thus be desirable to provide a relatively simplified method for forming an integrated device in which activation of the source and drain regions can be performed without adverse impact on the gate electrode.
One method for annealing source and drain regions without subjecting metal gates to destructive heating relies upon the use of relatively intense radiant energy generated by a laser or lamp, for example. However, the use of radiant energy for annealing the junction of an integrated device poses its own problems. By way of background to explain these problems,
FIG. 1
shows a cross-section of an integrated device, in this case a metal-insulator-semiconductor field-effect transistor (MISFET)
1
that is formed in an active region of the substrate that is bounded and electrically isolated by field isolation region
3
. A well region
4
is formed in the active region by introducing dopants into the semiconductor substrate
2
. A gate region
7
is fabricated on the substrate
2
by forming a gate insulator layer
8
and a gate conductor layer
9
, and patterning these layers by selective etching, for example, so that these layers overlie a limited portion of the active region that is to serve as the channel region of the integrated device
1
. Dopants of opposite type as that of the well region
4
are implanted in the active region to form the source region
5
and drain region
6
on opposite sides of the gate region
7
. To melt and recrystallize the source and drain regions
5
,
6
for activation, a laser or lamp is used to generate radiant energy
10
which is directed to the source and drain regions. As shown in
FIG. 1
, the fact that the gate region
7
extends higher than the source and drain regions
5
,
6
causes the radiant energy to be partially blocked in those portions of the source and drain regions
5
,
6
immediately adjacent the gate region
7
. Also, the relatively sharp features at the edges of gate region
7
cause the radiant energy
10
to diffract and generate interference patterns on the source and drain regions adjacent the gate. These shadowing and interference effects, represented by numeral
11
in
FIG. 1
, reduce the amount of radiant energy in the source and drain regions
5
,
6
near the gate region's edge as compared to portions of the source and drain regions that are relatively distant from the gate region's edge. The reduction of radiant energy absorption in the portions of the source and drain regions
5
,
6
adjacent the gate region
7
make it relatively difficult to melt such portions of the source and drain regions. Furthermore, at the portions of the source and drain regions
5
,
6
adjacent the field isolation regions
3
, the relatively poor thermal conductivity of the field isolation regions as well as optical interference effects, can lead to excessive melting beyond the desired source and drain boundaries into the substrate
2
, a problem that can adversely affect electrical isolation of the device and significantly degrade the device's performance. Thus, the fluence of the radiant energy used for the annealing step must be controlled within a relatively narrow range to affect melting of the edges of the source and drain regions
5
,
6
both near the field isolation region
3
and the gate region
7
without melting the underlying substrate
2
. Simultaneous achievement of these constraints in previous methods for forming an integrated device is typically very difficult, if not impossible. It would be desirable to provide a method in which annealing of the source and drain regions of a transistor can be performed with radiant energy so as not to melt the metal gate conductor layer
9
while achieving relatively uniform melting of the source and drain regions
5
,
6
to enhance the process margin available for successful performance of the method beyond that attainable with previous technologies.
SUMMARY OF THE INVENTION
Overcoming the above-noted disadvantages is the object of the present invention, and does in fact overcome such disadvantages. A preferred embodiment of the invented method includes forming a radiant energy absorber layer over a gate region of at least one transistor device, and irradiating the radiant energy absorber layer with radiant energy, preferably from a laser. The irradiating step generates heat in the radiant energy absorber layer that passes through the gate region to portions of the integrated device's source and drain regions that are adjacent to the gate region. The invented method permits the portions of the source and drain regions adjacent the gate region to be melted through transfer of heat from the radiant energy absorber layer to counteract shadowing and interference effects that limit the amount of radiant energy received by such portions of the source and drain regions. Melting and recrystallization through radiant energy irradiation can thus be performed more uniformly over the entire extent of the source and drain regions to significantly enhance the process margin available for activation annealing of the source and drain regions relative to previous methods.
The radiant energy absorber layer is composed of a material with a reflectivity that is lower than that of the source and drain regions. Preferably, the reflectivity of the radiant energy absorber layer is at least ten percent (10%) less than the reflectivity of the source and drain regions. This difference in reflectivity causes the temperature of the radiant energy absorber layer to be raised above that of the source and drain regions upon irradiation of the integrated transistor device with radiant energy to create a temperature gradient between the radiant energy absorber layer and the portions of the source and drain regions that are adjacent to the gate region. The temperature gradient causes heat to flow from the radiant energy absorber layer through the gate region to portions of the source and drain regions adjacent the gate region to permit such regions to be melted and recrystallized. The radiant energy absorber layer can be composed of a variety of substances with relatively high melting temperatures including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), tungsten (W), and platinum (Pt). Preferably, the radiant energy absorber layer is formed to a thickness that is sufficient to absorb at least ninety (90%) of the radiant energy incident to the radiant energy absorber layer. Generally, a thickness of from ten (10) to one-thousand (1,000) nanometers is sufficient to absorb this amount of incident radiant energy.
Talwar Somit
Verma Gaurav
Jones Allston L.
Pham Long
Ultratech Stepper, Inc.
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