Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-15
2001-12-11
Niebling, John F. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S239000
Reexamination Certificate
active
06329249
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of making a semiconductor device and, more particularly, to a method for forming different gate oxide layers in a single chip.
2. Description of Related Art
Recent trends toward high density integrated circuits increase the chip density while decreasing the size of the transistor built on the chip and decreasing gate oxide thickness.
FIG. 1
schematically shows the relationship between the electrical field (MV/cm) and the gate oxide thickness (Å) for a high voltage logic device and a normal voltage logic device. As can be seen, the probability of gate oxide breakdown increases with a decrease in gate oxide thickness. To avoid this problem, supply voltage (V
DD
), which is required to operate the chip, has been reduced. Since a reduced supply voltage causes degradation of power and speed, the thickness of the gate oxide layer has to be reduced to cope with this degradation of power and speed.
It is well known that transistor characteristics can be increased by reducing the gate oxide thickness, while at the same time keeping the supply voltage at a constant level. On the other hand, the power consumption can be reduced by decreasing the supply voltage, while keeping the gate oxide thickness at a constant level. Therefore, the gate oxide thickness must be reduced without breakdown thereof, while keeping a constant electric field. This phenomenon is commonly referred to as the “constant electric field scaling law.”
It is a recent trend in the DRAM or MDL industry to increase the chip areas occupied by the cell array. Therefore, if the gate oxide layers are formed to have the same thickness throughout the single chip, the gate oxide at the cell array region is subject to suffering from breakdown. Furthermore, since voltage (V
HDD
) exceeding supply voltage (V
DD
) is supplied to the cell array interior, the electric field applied thereto is increased, and this intensifies or increases the possibility of the gate oxide breakdown.
Since the cell density in the cell army region increases four folds per one generation, controlled threshold voltage is required against sub-threshold leakage and gate length variation, i.e., short channel effect margin is required. Besides short channel margin, drain saturation current (I
DSAT
) is required to be increased in the peripheral region.
To overcome some of the above-mentioned problems, several methods have been disclosed. One of them is to increase the doping concentration in the channel region so as to adjust the threshold voltage considering the short channel effect. The increase in the doping concentration, however, decreases the breakdown margin and increases the threshold voltage variation for a given gate length. In other words, gate length margins are reduced.
Another approach is to fabricate the cell array region and peripheral region on different chips, and not on a single chip. This method, however, has a disadvantage of requiring process complexity and is not compatible with low-cost fabrication.
SUMMARY OF THE INVENTION
The present invention was made in view of the above problem provides a method for forming different gate oxide layers in a single chip and, more particularly, provides a method for forming different gate oxide layers after formation of the gate electrode. One of the key features of this invention is to form different gate oxide layers through the oxidation process, which is dependent on the dimension of the active width The active width dependent oxidation process is carried out after formation of the complete transistor (formation of the sidewall spacers).
Different dimensions of the active areas (for example, cell array region and peripheral region) are defined in and on the semiconductor substrate. A first thin gate oxide layer is formed on the overall active areas with the same thickness. Different gate patterns are then formed over the thin oxide layer of the active areas. The gate patterns cross the active areas in parallel with the width direction. In the narrow active region, (cell array region), gate patterns are formed to have a narrow distance between adjacent gate patterns while having a wide distance between adjacent gate patterns in the wide region (peripheral region). Gate spacers are formed on lateral edges of the patterned gates. Critical wet oxidation can be carried out to thereby grow the thin oxide layer in the narrow active region (cell array region). The wet oxidation allows gate oxide growth to a greater extent in the narrow active region than the wide active region (peripheral region). Thus, different gate oxide layers are formed in one chip, i.e., a relatively thick gate oxide layer is formed in the cell array region and a relatively thin gate oxide layer is formed in the peripheral region.
During the oxidation process, oxidation along the gate length does not occur very easily, while oxidants can easily diffuse through the gate with which overlaps the field oxide layer. Therefore, if the active width is narrow (in the cell array region), the oxidant from the gate width direction (i e., from the field oxide) grows thickly in the thin gate oxide layer. On the other hand, if the active width is wide (in the peripheral region), the amount of the oxidant from the gate width direction is small considering the active size, so that the thickness variation of the thin gate oxide layer is negligible. Accordingly, different gate oxide layers are formed in one chip.
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C.Y. Wong, et al., Sidewall Oxidation of Polycrystalline-Silicon Gate, Sep. 1989, IEEE Electron Device Letters, vol. 10, No. 9, pp. 420-422.
Kim Ki-nam
Lee Jae-Kyu
Sim Jai-Hoon
Yang Won-suk
Niebling John F.
Samsung Electronics Co,. Ltd.
The Law Offices of Eugene M. Lee, PLLC
Whitmore Stacy
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