Contact structure using taper contact etching and polycide step

Details Contact structure using taper contact etching and polycide step Contact structure using taper contact etching and polycide step

1999-03-26

2001-04-03

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S755000, C257S774000, C257S900000

Reexamination Certificate

active

06211557

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to manufacturing of semiconductor devices in general, and in particular, to a new method for forming tapered contact openings by using a polycide step.
(2) Description of the Related Art
Making reliable contact with myriad of devices that are formed into a semiconductor substrate is one of the more difficult aspects of semiconductor manufacturing. The sub-micron devices are fabricated and isolated within a single-crystal substrate, and are further insulated by growing an oxide layer on the top surface of the substrate. The devices are then connected to form integrated circuits. The connections are accomplished by forming holes through the insulating layer and depositing high conductivity thin-film metal structures which in turn contact the underlying devices. As is well appreciated in the art, the geometry and size of the holes govern how well and reliably the contacts can be made. For example, if the walls of the hole are straight and vertical, then the metal that is deposited into the hole may not cover the edge of the hole properly. That is, the metal at the edge of the hole may be sharp and thin, giving rise to higher electrical resistance, or, for that matter, to breakage later on. In prior art, this is sometimes referred to as the “step coverage” problem and numerous methods have been devised to overcome it. Contouring the sidewalls or tapering the edge of the hole are some of the techniques that are used and are described below briefly. However, it will be seen that the conventional techniques are complex and complicated.
Following the well known art of forming a metal-semiconductor contact structure for an integrated circuit,
FIG. 1
a
shows a silicon substrate (
10
) with heavily doped region (
20
) extending into the silicon. The doped region represents areas of the substrate wafer, for example, where the source/drain of a MOS device would be formed and electrical contacts made. A “window” or contact hole is etched into an oxide layer (
30
) through a hole pattern in a photoresist mask (
40
) that covers the silicon wafer surface as shown in
FIG. 1
b
. Contact hole (
50
) is shown in
FIG. 1
c
after the mask has been removed. The oxide is typically a thermal oxide or chemical vapor deposited (CVD) oxide, while etching is an oxide removal process that can be accomplished by using either wet or dry etching as will be discussed further later. Prior to deposition of metal (
60
), the surface of the silicon wafer is cleaned to remove the thin native-oxide layer that rapidly forms on a silicon surface whenever it is exposed to oxygen, such as in air. Metal film (
60
) is deposited onto the wafer surface and makes contact with the silicon wherever contact holes have been formed in the oxide. In the simplest contact structure, the deposited metal is aluminum (Al) or an Al:Si alloy. For completeness, we note that after deposition, the contact structure is subjected to a thermal cycle known as sintering of annealing. The purpose of this step is to bring the metal and silicon surfaces into intimate contact. The nature and the area of the contact become important for small contact holes required with especially, submicron technologies.
Various methods are used for formation of contact hole windows. For relatively large openings greater than about 2.0 micrometers (&mgr;m), wet etching is often used. Its widespread use stems from the fact that the liquid etchant systems can be formulated to have very high selectivity to both the substrate and masking layers. That is, during the etching of contact holes in the oxide, neither the mask—which is usually a photoresist—nor the substrate materials are very much affected. The isotropic nature of wet etching, however, makes it difficult when etching smaller sized and closely patterned contact holes, especially for the sub-micron VLSI and ULSI (ultra large scale integrated) technologies. This is because, when etching progresses at the same rate in all directions, that is, isotropically, undercutting occurs if the thickness of the film layer that is being etched is comparable to the minimum pattern dimensions. Of course, undercutting between small and closely spaced holes would be intolerable. Hence, since many films used in VLSI fabrication are 0.5-1.0 &mgr;m thick, reproducible and controllable transfer of patterns in the 1-2 &mgr;m range becomes difficult if not impossible with wet etching, according to S. Wolf in his book “Silicon Processing for the VLSI Era,” vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 539. As is well known, an alternative to “wet” etching is the “dry” etching which offers the capability of anisotropic removal of material. Dry etching essentially consists of “ion assisted etching processes” of which reactive ion etching (RIE) providing anisotropic etching, and plasma etching providing isotropic etching are well known.
Though anisotropic etching is useful because it avoids undercutting, that is not always desirable for the reasons indicated in FIG.
1
. When the sidewalls of hole (
50
) are formed vertically as shown in
FIG. 1
by dry etching, the step edge (
55
) of the hole is not usually well covered when the hole is later filled with metal (
60
). Poor step coverage can lead to electrical discontinuities. This problem can sometimes be alleviated by first using wet or dry isotropic etching in region (
70
) and then following it with anisotropic etching in region (
80
) as shown in FIG.
2
. The resulting hole geometry is contoured as shown in the same Figure rather than being straight and vertical.
Another approach for sidewall contouring involves the manipulation of the photoresist mask. This is accomplished by controlling the erosion of photoresist that has been baked to produce a sloped photoresist wall. The contact hole pattern on the photoresist are exposed and developed using standard lithographic techniques as explained in Wolf, p. 105 and shown in
FIG. 3
a
. Following develop step, the patterned resist images (
40
) are subjected to a postdevelop bake. The resist flows during the bake, relaxing the vertical resist profile (
FIG. 3
b
). Etching the resist (
40
) and oxide (
30
) at approximately the same rate replicates the tapered-resist profile into the contact hole (
50
) sidewall as shown in
FIG. 3
c
. It will be known to those skilled in the art that anisotropic etching recipes can be modified to etch in different rates laterally and in vertical direction.
It is clear from cited prior art that almost all different parts that go into making a contact hole, such as the photoresist, the oxide and the elements of etching—isotropic, anisotropic—have been manipulated in one way or another to achieve a desired contact hole. However, the processes are complicated and complex. Still another method proposed in U.S. Pat. No. 5,490,901 involves the use of several masks for forming a contact hole in a semiconductor device exhibiting elevated topology. This adds further to the complexity by introducing additional masks. In the present invention, a simple and relatively easy method is disclosed where the number of process steps are reduced and the reliability of the contact hole so formed is improved.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a new method for forming tapered contact holes in semiconductor devices.
It is another object of this invention to reduce the number of steps in forming contact holes in semiconductor devices.
It is still another object of this invention to provide a method for improving the reliability of contact holes through widened isolation windows.
These objects are accomplished by providing a silicon substrate having active and field regions defined, gate oxide formed and depositing a multilayer polycide over the surface of the substrate. Polycide is chosen to be a multilayer structure comprising a tungsten-silicide (WSi
2
) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi
2
faster than it etches the

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