Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-16
2001-08-07
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S254000
Reexamination Certificate
active
06271084
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a metal-insulator-metal (MIM), capacitor structure for a dynamic random access memory (DRAM), device.
(2) Description of Prior Art
The ability to merge DRAM arrays with logic circuits require complex process integration, in addition to the process difficulties encountered as a result of the topology created by the DRAM capacitor structures. The formation of crown shaped, DRAM capacitor structures, prior to formation of first level metal interconnections, require thick insulator layers to successfully cover the topology created by the DRAM capacitor structures. However the use of thick insulator layers, needed for coverage of the DRAM capacitor structures, requires the use for high aspect ratio contact openings, in the logic region. The use of high aspect ratio contact holes present process difficulties in terms of dry etching through the thick insulator layers, as well as difficulties encountered during the metal filling of the narrow diameter, deep openings. These process difficulties can result in yield loss for the logic chips comprised with embedded DRAM arrays. This invention will describe a fabrication process in which DRAM arrays are embedded in logic circuits, however with the DRAM devices featuring the use of a damascene procedure to fabricate a metal-insulator-metal (MIM), DRAM capacitor structure, thus alleviating the severe topology, and the process difficulties associated with this topology, created when using conventional crown shaped, DRAM capacitor structures. Prior art, such as Lee et al, in U.S. Pat. No. 5,918,135, as well as Nishikawa et al, in U.S. Pat. No. 6,087,261, describe the fabrication of MIM capacitor structures, however these prior arts do not describe the integration of embedded DRAM arrays with logic circuits, and do not describe the novel damascene process, described in the present invention, which allows reduced topology to be realized, thus reducing process complexity, for embedded DRAM array designs.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a fabrication procedure for vertical MIM capacitor structures used in an embedded DRAM technology.
It is another object of this invention to reduce the topology created by DRAM capacitor structure via use of a damascene procedure used for fabrication of the vertical MIM capacitor structure, and via the formation of the DRAM, MIM capacitor structure performed after fabrication of the first metal interconnect structure.
It is still another object of this invention to use low temperature procedures for fabrication of the DRAM MIM capacitor structure, reducing the thermal impact on the logic device performance.
In accordance with the present invention a method of integrating the fabrication of DRAM devices with the fabrication of logic circuits, featuring vertical DRAM, MIM capacitor structures formed using a damascene process, has been developed. After formation of the transfer gate transistors for both the logic circuit and DRAM arrays, damascene type, first level metal interconnect structures are formed, contacting regions of the underlying transfer gate transistors. A composite insulator layer, comprised of an underlying insulator stop layer, a low k dielectric layer, and an overlying insulator stop layer, is deposited, followed by the formation of capacitor openings in the overlying stop layer, and in the low k dielectric layer of the composite insulator layer. An isotropic etch is next used to laterally recess the low k dielectric layer, in the capacitor opening. After removal of the portion of underlying stop layer, exposed in the capacitor opening, a bottom electrode layer is deposited, overlying and contacting the surface of the first level metal interconnect structure. An organic layer is used to protect the region of the bottom electrode layer residing in the capacitor opening, allowing the portion of the bottom electrode layer residing on the top surface of the overlying insulator stop layer to be removed, defining the bottom electrode structure. After formation of a capacitor dielectric layer, on the bottom electrode structure a conductive layer is deposited, completely filling the capacitor opening, then subjected to a chemical mechanical polishing procedure, to create a damascene type, top electrode, overlying the capacitor dielectric layer, in the capacitor opening. A damascene type, second level metal interconnect structure is then formed overlying and contacting the vertical MIM capacitor structure, residing in the capacitor opening.
REFERENCES:
patent: 5518948 (1996-05-01), Walker
patent: 5918135 (1999-06-01), Lee et al.
patent: 6074913 (2000-06-01), Lou et al.
patent: 6087261 (2000-07-01), Nishikawa et al.
patent: 6184081 (2001-02-01), Jeng et al.
Chi Min-hwa
Tsai Chia-Shiung
Tu Yeur-Luen
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tsai Jey
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