Method of manufacturing bottom electrode of capacitor

Details Method of manufacturing bottom electrode of capacitor Method of manufacturing bottom electrode of capacitor

1999-04-20

2001-05-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000

Reexamination Certificate

active

06225160

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing an integrated circuit. More particularly, the present invention relates to a method of manufacturing a bottom electrode of a capacitor of a DRAM.
2. Description of the Related Art
Typically, in order to meet the requirement of reducing the size of integrated circuits (ICs), a method used to increase the surface area of the capacitor on a substrate with a fixed surface area is developed. The method is to form a hemispherical grained (HSG) structure on the surface of the substrate to increase the surface area of the capacitor. A DRAM is taken as an example. When data are read by an amplifier, the more the charges in the capacitor of the DRAM are, the smaller the interference cause by the noise is. Moreover, the frequency for refreshing the storage charges is greatly reduced. Commonly, the method for fabricating the hemispherical grains in the ICs manufacturing process comprises forming a HSG layer on an amorphous silicon surface of a wafer selectively. Since the hemispherical grains are selectively formed, those can be called selective hemispherical grains.
FIG. 1
is schematic, cross-sectional view of a conventional bottom electrode of a capacitor with a HSG layer. As shown in
FIG. 1
, an oxide layer
110
is formed on a substrate
100
having previously formed field effect transistors
104
by chemical vapor deposition (CVD). A node contact hole
112
is formed to penetrate through the oxide layer
110
and exposing a portion of a source/drain region
108
of the field effect transistors
104
. A doped amorphous silicon layer (not shown) is formed over the substrate
100
and fills the node contact hole
112
. The doped amorphous silicon layer is patterned to form a doped amorphous silicon layer
114
used as a bottom electrode of the capacitor. A selective HSF layer
116
is formed on the doped amorphous silicon layer
114
to increase the surface area of the bottom electrode.
When the oxide layer
110
is formed by CVD, the oxide layer has many impurities such as hydrocarbon-bonds containing impurities. These impurities easily volatilize in the subsequent high temperature manufacturing steps. When the impurity vapor volatilizes from inside the oxide layer
110
to the surface thereof, outgassing happens.
Typically, high vacuum conditions must be maintained during the formation procedure of the HSG layer
116
. When outgassing occurs during the formation procedure of the HSG layer
116
, the vacuum quality of the furnace or the reaction chamber isadversely affected. Therefore, it is difficult to perform the nucleation to form hemispherical grain s and the migration of the silicon atoms of the doped amorphous silicon layer
114
is also difficult. Hence, there are relatively fewer hemispherical grains and these hemispherical grains are relatively smaller. Therefore, the increase in surface area for the bottom electrode is limited.
Additionally, after the HSG layer
116
is formed, the native oxide layer (not shown) formed on the HSG layer
116
and the amorphous silicon layer
114
is removed by hydrofluoric acid. Then, the steps of forming a dielectric layer (not shown) and forming an upper electrode are performed. In order to completely remove the native oxide layer, an overetching process is performed. However, hydrofluoric acid also etches the oxide layer
110
, so that a recess
118
in the oxide layer
110
due to the overetching with hydrofluoric acid easily occurs. Therefore, the reliability of the device is decreased. Moreover, it has no restraining layer on the oxide layer
110
to resist charge migration along the oxide layer
110
. Therefore, a gate oxide layer (not shown) can easily capture the charges, so that the gate oxide layer decays.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a bottom electrode of a capacitor to avoid outgassing and to improve the quality of the hemispherical grains formed on the bottom electrode. Additionally, by using the invention, the recess in the dielectric layer caused by the overetching process can be avoided. Moreover, the gate electrode can be prevented from collapsing.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer. Since the cap layer is formed on the first dielectric layer, the recess in the first dielectric layer caused by overetching will not occur. Moreover, the cap layer can restrain charge penetration and charge migration along the first dielectric layer, so that a gate electrode of a device can be prevented from collapsing. Additionally, because the material of the cap layer, the liner layer and the restraining layer can restrain outgassing from occurring at the first and the second dielectric layers while the patterned conductive layer and the selective hemispherical grained layer are formed, the quality of the selective hemispherical grained layer is relatively good.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6066893 (2000-05-01), Wise

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