Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-07
2001-08-07
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000
Reexamination Certificate
active
06271073
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the fabrication of semiconductor memory devices and, more specifically, to a method of forming transistors in a peripheral circuit of a random access memory device.
BACKGROUND OF THE INVENTION
Generally, integrated circuits are mass produced by forming many identical circuit patterns on a single silicon wafer. Integrated circuits, also commonly referred to as semiconductor devices, are made of various materials that may be electrically conductive, electrically nonconductive (insulators) or electrically semiconductive. It is advantageous to reduce the number of steps in the fabrication process to reduce fabrication costs and increase quality and reliability, since the opportunities for the occurrence of disabling defects is reduced. In this way, electronic equipment becomes more reliable, assembly and packaging costs are minimized and circuit performance is improved.
Random access memory devices such as Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs) include memory cells for storing data and peripheral circuits for switching signals in and out of the memory cells. It is desirable to form the transistors in the peripheral circuits at the same time transistors, capacitors and other components are formed in the memory cell array to minimize the number of processing steps necessary for fabrication of the entire device. During formation of the memory cells, layers of polysilicon and oxide insulators are deposited, patterned and etched to form the memory cell components. At the same time, these polysilicon and oxide layers are also being deposited and, to some extent, further processed in the area of the chip where the peripheral circuit transistors are formed. The efficiency of the overall process flow is enhanced to the extent the formation of transistors in the peripheral circuit can be integrated into the formation of memory cell components.
SUMMARY OF THE INVENTION
The general purpose and principal object of the present invention is to provide a method that integrates the formation of transistors in the peripheral circuit with the formation of resistors, capacitors and other components in the memory cell array of semiconductor memory devices.
To accomplish the above and other objects, there has been developed a method of forming a transistor in a peripheral circuit of a random access memory device which includes the steps of forming over a substrate in a memory cell array region and in a peripheral region, a gate oxide layer and at least one polysilicon layer over the gate oxide layer, and then patterning and etching the polysilicon layer(s) to simultaneously form a resistor, capacitor electrode or other component in the array region and a periphery transistor gate in the peripheral region.
In one aspect of the invention, the periphery transistor gate is formed simultaneously with the formation of a load resistor in the memory cell array of a Static Random Access Memory (SRAM). In this aspect of the invention, the step of patterning and etching a polysilicon layer in the peripheral region is performed simultaneously with and as part of the patterning and etching of a polysilicon layer in the memory cell array region during which the formation of the load resistor is completed. Alternatively, the periphery gate may be formed simultaneously with the formation of the ground line and bitline contact landing pad in the SRAM memory cell array region. That is, the step of patterning and etching a polysilicon layer in the peripheral region is performed simultaneously with and as part of the patterning and etching of a polysilicon layer in the memory cell array region whereby the ground line and bitline contact landing pad is formed.
In another aspect of the invention, the periphery transistor gate is formed simultaneously with the formation of a capacitor electrode in the memory cell array region of a Dynamic Random Access Memory (DRAM). In this aspect of the invention, the step of patterning and etching a polysilicon layer in the peripheral region is performed simultaneously with and as part of the patterning and etching of a polysilicon layer in the memory cell array region during which a capacitor electrode is formed.
The foregoing and other objects, advantages and novel features of the invention will become apparent to those skilled in the art from the following detailed description wherein I have shown and described only the preferred embodiments of the invention simply by way of illustrating the best mode contemplated by me of carrying out the invention. The invention is capable of other and different embodiments and use in other applications, and its several details are capable of modifications in various obvious respects, all without departing from the scope and spirit of the invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not as restrictive.
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Micro)n Technology, Inc.
Ormiston & McKinney PLLC
Tsai Jey
LandOfFree
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