Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1997-12-05
2001-04-24
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C324S1540PB, C326S046000
Reexamination Certificate
active
06223313
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to application specific integrated circuits (ASICs), and more specifically, the invention relates to testing gate arrays.
BACKGROUND OF THE INVENTION
Use of ASICs has become widespread in the semiconductor industry as giving circuit design engineers a relatively high amount of circuit functionality in a relatively small package. In particular, ASICs are customizable integrated circuits that are customized to implement a circuit specified by a design engineer (a “user-designed circuit”). One type of ASIC is the gate array, which generally includes an array of function blocks, each of which are predesigned and/or prefabricated to include a particular number, arrangement, and type of semiconductor devices, e.g., transistors. To customize a gate array to implement a particular user-designed circuit specified by a design engineer, various connections are made among the semiconductor devices within the function block and/or various connections are made among function blocks (i.e., routing is customized).
ASICs, including gate arrays, once customized to implement a user-designed circuit, must be tested to ensure that the user-designed circuit operates properly. Tests must be able to detect faults, which are the results of defects (physical problems with the circuit, e.g., shorts, and/or improper circuit design), resulting in improper or unexpected circuit behavior.
Faults include “Stuck At Faults” (SAFs), delay faults and current faults. SAFs occur when a particular connection in the circuit remains at (is “stuck” at) a logical low level or a logical high level regardless of what signals are applied to the circuit. (As used herein, “logical low” refers to a “0” signal, which is often a ground signal. A “logical high” refers to a “1” signal, which is often a V
DD
signal.) Delay faults occur when the circuit is designed to accommodate a particular propagation time, but the circuit actually operates much slower than expected. For instance, if a circuit was designed with the belief that there would only be a 5 ns propagation time of a signal between a first point and a second point, but in operation the signal actually takes 15 ns to propagate from the first point to the second point, the circuit may not operate properly. Current faults will often occur in circuits utilizing CMOS devices, which are not supposed to draw current when inactive, but do. The defects that cause current faults can frequently be detected by testing for SAFs.
Well-designed tests of an integrated circuit will generally be able to detect most SAFs at the gate level (i.e., the conceptual circuit design level containing Boolean logic, flip-flops, etc.) by testing all connections between logic elements. In order to test all connections between logic elements, the tester needs to be able to both (1) control, or set, the value at a particular connection and (2) be able to observe the value at the particular connection. For instance, in order to test the connection between point A and point B for Stuck At 0 faults, the tester needs to be able to apply stimulus data that ought to place a logical high on the connection line, and then the tester needs to be able to observe the connection to see if and how the value changes as a result of the stimulus data.
In discrete circuit design, the ability to control and observe a particular circuit is often done by simply probing the various connections among the logic elements of the circuit. However, with integrated circuits, the ability to probe connections internal to the circuit is generally unavailable and other methods of testing have had to be developed as a result.
One method of testing an integrated circuit that enjoys the most popularity among IC designers is “scan” testing, which will be described with reference to the block diagrams of
FIGS. 1 and 1
a.
In
FIG. 1
, circuit
102
is generally composed of any number and arrangement of logic elements (e.g., Boolean logic gates, flip-flops, latches, etc.) and has input A and output B. Inputs A can be coupled directly to flip-flops
104
(via lines
114
) or to other logic elements in logic
102
. Likewise, outputs from flip-flops
104
can be coupled directly to outputs B (via lines
112
), to other logic elements in logic
102
, or directly to other flip-flop
104
inputs. Each flip-flop
104
contained in circuit
102
is coupled to a clock signal such as CLK
1
108
or CLK
2
109
. The flip-flops
104
, shown apart from the circuit
102
for illustrative purposes only, will each, upon receiving a triggering clock edge, store a value and hold the value on its respective output until a next triggering clock edge is received. Therefore the flip-flops of circuit
102
collectively represent the state of the circuit: at any time when the clocks are stopped, the flip-flops will maintain the state of the circuit.
By taking advantage of the state-machine nature of the circuit, the state of the circuit
102
can be controlled for test purposes by placing known values into the flip-flops
104
. Similarly, the state of the circuit can also be observed by reading the values held in the flip-flops after the circuit has been run. In order to control and observe the values held in flip-flops
104
of the circuit
102
, the flip-flops
104
are, in addition to their regular circuit connections represented by lines
112
and
114
, coupled to one another in a daisy-chain fashion, i.e., the output of one flip-flop is coupled to the input of the next flip-flop, as generally shown in
FIG. 1
a.
Furthermore, clock steering logic, such as multiplexer
111
, is frequently inserted so that all testing and shifting can be effected with one clock signal. To test logic circuit
102
, the regular “mission mode” operation of circuit
102
is stopped and a series of stimulus values are shifted into flip-flops
104
, via the daisy-chain, so that each flip-flop in logic circuit
102
has a known value. Stimulus values are shifted in by applying the stimulus values one at a time to the input
106
of the first flip-flop in the daisy-chain and running the circuit clock
108
(coupled to the clock input of each flip-flop
104
) to propagate the values through the daisy-chain. After the flip-flops
104
have each received a known test value, the circuit
102
is then exercised (run normally) for a brief period, e.g., one clock cycle, and then stopped. The state of the circuit resulting from its being run is captured in flip-flops
104
. The resulting values are then shifted out of the flip-flops
104
, by again running the clock
108
and reading the values at the output
110
of the last flip-flop in the daisy-chain.
More specifically, to implement scan-type testing, typically one of two techniques is used: mux-based scan or clock-based scan. “Mux-based scan” is the more commonly used technique and is described with reference to the block diagram of FIG.
2
. Clock-based scan will be described with reference to FIG.
3
.
As shown in
FIG. 2
, for each flip-flop
104
n
in the logic circuit
102
, (where flip-flops
104
are shown apart from circuit
102
for illustrative purposes only) a 2-input multiplexor
212
n
is placed at the D-input of each respective flip-flop
104
n
. One input, e.g., the 0 input, for each multiplexor
212
n
receives the regular connection
114
from the logic
102
that would otherwise go directly into the D-input but for the multiplexor
212
n
. The second input, e.g., the 1 input, of each multiplexor
212
n
is coupled to the output of a flip-flop
104
n+1
, thereby daisy-chaining the flip-flops. As shown in
FIG. 2
, the Q-output of flip-flop
104
2
is coupled to the 1-input of multiplexor
212
1
, and the Q-output of flip-flop
104
1
would be coupled to another multiplexor
212
0
(not shown). The 1-input to multiplexor
212
2
would be received from the Q-output of flip-flop
104
3
(not shown). A circuit clock line (CLK)
108
is coupled to each of the flip-flops
104
n
as it would be without inclusion of multiplexors
212
n
. A SHIFT signal
214
is coupled
How Dana
Mukund Shridhar
Osann Robert
Srinivasan Adi
Fliesler Dubb Meyer & Lovejoy LLP
Lightspeed Semiconductor Corporation
Moise Emmanuel L.
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