Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-16
2001-03-27
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S644000
Reexamination Certificate
active
06207989
ABSTRACT:
FIELD OF THE INVENTION
This invention relates, in general, to non-volatile memory devices and more particularly, to non-volatile memory devices having composite insulation layers.
BACKGROUND OF THE INVENTION
State of the art non-volatile memory devices are typically constructed by fabricating a floating-gate transistor in a silicon substrate. The floating-gate transistor is capable of storing electrical charge either on a separate gate electrode, known as a floating-gate, or in a dielectric layer underlying a control gate electrode. Data is stored in a non-volatile memory device by the storage of electrical charge in the floating-gate. For example, in an n-channel EEPROM (electrically-erasable-programmable-read-only-memory) device, an accumulation of electrons in a floating-gate electrode changes the threshold voltage in the floating-gate transistor.
One particular type of non-volatile memory device is the flash EEPROM. In a flash EEPROM device, electrons are transferred to the floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode. In one type of device, the control-gate electrode is a polycrystalline silicon gate electrode overlying the floating-gate electrode, and separated therefrom by a dielectric layer. In another type of device, the floating-gate electrode is a doped region in the semiconductor substrate.
The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region of the floating-gate transistor. These applied potentials transfer electrons from the substrate through the tunnel oxide layer and to the floating-gate electrode. Conversely, the EEPROM device is erased by grounding the control-gate electrode, and applying a high positive voltage to either the source or drain region of the floating-gate transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and enter either source or drain regions in the semiconductor substrate.
Another type of EEPROM device is extensively used in programmable logic devices (PLDs). EEPROM cells formed in PLDs include three transistors: a write transistor, a read transistor, and a sense transistor. In PLD EEPROM cells, the control gates of the write transistor and read transistor are connected to the same wordline. Also, in PLD EEPROM cells, the read transistor and the sense transistor are connected to the same bitline. When the read transistor is turned on, the common bitline connection permits the sense transistor to be effectively used as the storage cell of the EEPROM.
In operation, to program PLD EEPROMs, a high voltage (between 13 and 15 volts) is applied to the wordline of the EEPROM cell. A relatively high voltage (approximately 11 to 12 volts) is applied to the control gate of the write transistor, allowing voltage applied on the bitline to be transferred to the control gate of the sense transistor. The application of such high voltage levels is a write condition that results in data being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage V
cc
is applied to the wordline of the write transistor, which also causes the read transistor to turn on. Ground potential is applied to the bitline, which is connected to the drain of the read transistor. A high voltage (between 13 to 15 volts) is applied on the capacitor coupled control gate (ACG). Under this bias condition, the high voltage applied to ACG is coupled to the floating-gate of the sense transistor and the EEPROM cell is erased by the transfer of electrons through the tunnel oxide layer from the floating-gate to the substrate.
It is known that charge loss from a floating gate of a cell of a non-volatile memory device or a PLD is caused, in part, by positive ions (such as hydrogen) which are disposed in the oxide layer surrounding the floating gate. These positive ions are free to combine with electrons collected on the floating-gate. The combination of positive ions with electrons results in a net charge loss from the floating-gate and weakens the data retention capability of a non-volatile memory device or a PLD. It is widely believed that high temperatures (e.g., temperatures above 200° C.) increase the diffusivity of such positive ions in the oxide layer, which increases the rate of ion-electron combinations thereby accelerating the charge loss from the floating-gate. When charge leaks off the floating-gate electrode, a data error occurs in the memory cell.
In addition to charge loss, data errors can also arise from excess charge accumulation of the floating-gate. Unwanted capacitive coupling with electrically conductive structures in close proximity to the floating-gate can induce excess charge build up in the floating-gate. The accumulation of charge cases the threshold voltage of the floating-gate transition (or the sense transistor in a PLD) to shift away from the originally designed valve. Once the threshold voltage shifts away from the designed value, the floating-gate transistor cannot be turned on by application of a typical read voltage applied to the floating-gate electrode. When this happens, a read error occurs and an incorrect logic signal is transmitted from the memory cell.
Both charge leakage and threshold voltage instability produce data errors during operation of the EEPROM cell. Depending upon the particular function performed by the non-volatile memory device, the data error can cause catastrophic failure in an electronic system relying upon the device. Accordingly, an improved non-volatile memory device is necessary to provide a high-reliability device that exhibits stable threshold voltage values.
SUMMARY OF THE INVENTION
The present invention is for a non-volatile memory device having a high-reliability composite insulation layer that exhibits improved data retention. The device includes a composite insulation layer that getters mobile ions, such as hydrogen ions, introduced into the device during processing. The composite insulation layer is designed to getter mobile ions, while avoiding capacitative coupling with the floating-gate electrode. The relative thicknesses of the individual layers within the composite insulation layer are precisely determined, such that the layer gettering mobile ions is sufficiently proximate to the floating-gate electrode to prevent mobile ions from diffusing to the floating-gate electrode. Additionally, the relative thicknesses of the individual layers within the composite insulation layer are defined so as to provide dielectric insulation between the gettering source and the floating-gate electrode. The dielectric insulation is necessary to avoid capacitative coupling of the gettering source with the floating-gate electrode. Capacitative coupling of the gettering source with the floating-gate electrode can result in undesirable charge buildup within the floating-gate electrode.
In one form, a semiconductor substrate is provided having a device layer thereon. A composite insulation layer overlies the device layer. The composite insulation layer includes a first undoped dielectric layer, a doped insulating layer overlying the first undoped dielectric layer, and a second undoped dielectric layer overlying the doped insulating layer. The first undoped dielectric layer has a thickness of about 450 to about 550 Å, the doped insulating layer has a thickness of about 2900 to about 3100 Å, and the second undoped dielectric layer has a thickness of about 6000 to 8000 Å.
REFERENCES:
patent: 4818335 (1989-04-01), Karnett
patent: 5485035 (1996-01-01), Lin
Li Xiao-Yu
Mehta Sunil D.
Brinks Hofer Gilson & Lione
Crane Sara
Tran Thien F.
Vantis Corporation
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