Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-27
2001-04-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000
Reexamination Certificate
active
06214682
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of lightly doped source and drain regions for low resistance, ultra-shallow junctions.
2) Description of the Prior Art
As microelectronic device dimensions decrease, the need to produce ultra-shallow (<60 nm) junctions with low resistance becomes essential. However, conventional ion implantation and annealing processes present several obstacles to formation of ultra-shallow lightly doped source and drain regions necessary for acheiving ultra-shallow junctions with low resistance.
One method of forming ultra-shallow lightly doped source and drain regions is to form a screen oxide layer, implant impurity ions through the screen oxide layer, then perform an anneal to drive in the impurity ions. The disadvantage of this process is that it is susceptible to oxygen enhanced diffusion (OED). OED causes “B” ions to diffuse deeper into the silicon substrate when a screen oxide is used even though the implant depth is shallower than without a screen oxide.
Another process used to form lightly doped source and drain regions is to perform an ion implant and pure N
2
drive in without using a screen oxide. This process does not suffer from OED. However, surface dopant loss occurs during the post implant anneal to drive in the impurity ions. Also, due to reduced gate oxide thicknesses associated with reduced scale devices, the lack of a screen oxide can cause gate oxide integrity degradation due to implantation damage.
An alternate approach is to form a screen oxide, perform impurity ion implantation, strip the screen oxide, then anneal to drive in the impurity ions. Since the screen oxide is removed prior to anneal, this process also suffers from surface dopant loss. Although the screen oxide prevents gate oxide degradation due to implantation damage, oxide stipping can also degrade the gate oxide integrity.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,525,529 (Guldi) discloses forming a source and drain region using a screen oxide or screen oxynitride blocking layer and an NH
3
anneal after ion implantation.
U.S. Pat. No. 5,604,854 (Yoo) and U.S. Pat. No. 5,792,699 (Tsui) teach standard LDD anneals.
U.S. Pat. No. 5,296,411 (Gardner et al.) shows a nitridation process to produce reliable oxides.
The following technical literature also provide information on relevant technical developments.
Privitera et al., Role of Surface and of Dopant Impurity Interactions on the Electrical Activation of B implant in Crystalline Si, Applied Physics Letters, Vol. 72, No. 23, 8 June 1998, pp. 3011 to 3013, teaches that while transient enhanced diffusion (TED) decreases at lower implant energy (typical of LDD), activation ratio also decreases as at lower implant energy.
Chao et al., Spicies and Dose Dependence of I/I Damage Induced Transient Enhanced Diffusion, Journal of Applied Physics 79(5), Mar. 1, 1996, pp. 2352 to 2363, discloses implant species dependance of diffusion due to point defect and dopant impurity interactions, particularly dopant clustering. However, species dependance of diffusion is less significant for lower doses.
L. H. Zhang et al., Transient Enhanced Diffusion without {311} Defects in Low Energy B+ Implantation, Applied Physics Letters, Vol. 67, No. 14, Oct. 2, 1995, pp. 2025 to 2027, discloses that for low energy (4 KeV) low dose (10
14
cm
−2
) TED diffusion occurs independent of anneal temperature, and apparently without 311 defects.
Segawa et al., A 0.18 &mgr;m Ti-Salicided p-MOSFET with Shallow Junctions Fabricated by Rapid Thermal Processing in an NH
3
Ambient, IEDM 96, pp. 443 to 446, discloses that nitrogen ions diffuse into the substrate at the projected range of B+ implantation for source/drain regions during rapid thermal processing in an NH
3
atmosphere, suppressing boron diffusion.
Downey et al., RTP Requirements for Annealing Ultra-Shallow Junctions, Varian—Report No. 298, teaches that while BF
2
shows dopant loss at lower temperature than B (950° C. vs. 1050°) that BF
2
is preferable for shallow junctions reducing the junction depth by 428 Å compared to B.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions having low resistance.
It is another object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions which reduces transient enhanced diffusion (TED).
It is another object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions which prevents surface dopant loss.
It is another object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions with a high activation ratio.
It is yet another object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions which prevents gate oxide integrity degradation.
To accomplish the above objectives, the present invention provides a method for fabricating ultra-shallow lightly doped source and drain regions (
14
,
16
). The process begins by providing a substrate (
10
) having a gate (
11
) thereon. A screen oxide layer (
12
) is formed on the substrate (
10
). P-type impurity ions are implanted into the substrate (
10
), through the screen oxide layer (
12
) to form lightly doped source and drain regions (
14
,
16
) adjacent to the gate. A post-implant anneal is performed on the lightly doped source and drain regions (
14
,
16
) using a rapid thermal anneal in a nitrogen containing atmosphere (e.g. NO, N
2
O, NH
3
) to drive in the impurity ions. The anneal in a nitrogen containing atmosphere introduces N ions into the substrate forming vacancies. The vacancies capture intersticial Silicon, reducing transient enhanced diffusion. The vacancies also help dissolve dopant complexes, increasing the activation ratio.
The present invention provides considerable improvement over the prior art. The ultra-shallow lightly doped source and drain fabrication method of the present invention can simultaneously reduce transient enhanced diffusion (TED) and increase the activation ratio. N ions are injected into the substrate in the source and drain regions during rapid thermal anneal in NH
3
. The N ions form vacancies which recombine with interstitial silicon, suppressing TED. The vacancies also help to dissolve impurity ion and defect complexes increasing the activation ratio.
Another advantage of the present invention is that the screen oxide layer acts as a cap layer reducing surface dopant loss and gate oxide degradation during post-implant annealing. Surface dopant loss increases resistance in lightly doped source and drain regions. Gate oxide degradation lowers the threshhold voltage of the gate.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5296411 (1994-03-01), Gardner et al.
patent: 5525296 (1996-06-01), Guldi
patent: 5605854 (1997-02-01), Yoo
patent: 5736446 (1998-04-01), Wu
patent: 5792699 (1998-08-01), Tsui
patent: 5960322 (1999-09-01), Xiang et al.
patent: 5994747 (1999-11-01), Wu
patent: 6008098 (1999-12-01), Pramanick et al.
patent: 6022785 (2000-02-01), Yeh et al.
Privitera et al., “Role of Surface and of Dopang-Impurity Interactions of the Electrical Activation of B Implants in Crystalline Si”, Applied Physics Letters, vol. 72, No. 23, Jun.
Ackerman Stephen B.
Le Dung A
Nelms David
Saile George O.
Stoffel William J.
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