Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2000-09-08
2001-08-14
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S787000, C438S788000
Reexamination Certificate
active
06274512
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-257699, filed Sep. 10, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device which eliminates a damaged layer formed on the surface of a silicon substrate by a plasma treatment.
In order to achieve a high-speed high-function semiconductor device, a growing demand has been made for the microminiaturization of individual semiconductor devices and their large-sized integration as time goes on. However, various difficulties are involved in the microminiaturization of a MOSFET constituting a major element of these semiconductor device.
For example, a problem of the so-called “short channel effect” arises due to a drop of a threshold level voltage resulting from the reduction of the channel length of the MOSFET. If a device whose threshold level voltage is different from a desired one is formed at a time of designing a semiconductor circuit, then the device operates in a way other than an intended design, thus damaging the function of an involved circuit as a whole.
Such short channel effect is due to the fact that the distortion of an electric field in the source/drain regions of the MOSFET imparts an adverse influence to a channel portion. This adverse influence can be avoided by bringing the position of a pn junction at an interface between the source/drain region and the semiconductor substrate nearer to the semiconductor surface, that is, by making the pn junction shallower.
If, however, the pn junction is made simply shallower, a resistance across the source/drain regions is increased, preventing a high-speed transmission of a signal propagating through the device. Further if a contact is provided so as to obtain electric contact on the source/drain regions, a metal material constituting that contact is diffused downwardly and punches through the junction and there is a risk that it will induce a junction leak. It may be possible to partially form an upper portion of the source/drain region with an alloy with a metal (silicide) so as to achieve a low resistance source/drain electrode. In this case, however, metal atoms are diffused into the source/drain regions and are liable to reach the junction portion.
In order to deal with such a problem, the so-called elevated source/drain structure has conventionally been proposed in which a semiconductor material is additively formed selectively on a silicon substrate surface portion corresponding to the source/drain region formation area to move the surface upwardly from the surface of the silicon substrate and, through the additively formed surface, a pn junction of the source/drain regions is formed. The elevated source/drain structure can secure the thickness of the source/drain region while achieving a shallower junction position than an original semiconductor substrate surface.
An explanation will be made below about the manufacturing steps of a MOS transistor having an elevated source/drain structure.
FIGS. 5A
to
5
E are cross-sectional views showing the steps of manufacturing a MOS transistor having a conventional elevated source/drain structure.
As shown in
FIG. 5A
, first, a gate insulating film
11
and gate electrode
12
are formed over an Si substrate
10
and then an n
−
diffusion layer
13
is formed. An insulating film
15
is deposited on a whole surface. Then, as shown in
FIG. 5B
, the insulating film
15
is subjected to RIE to form a sidewall insulating film
15
. At the time of the RIE, ions or radicals are generated from gas species in the etching gas, causing them to be introduced as an impurity into an underlying Si substrate or causing a lattice defect in a substrate crystal. As a result, a defective (damaged) layer
16
is formed in the Si substrate and gate electrode surface.
A selective growth of the silicon layer is very sensitive to the surface state on which the selective growth occurs. For example, the thickness of a Si film formed varies depending upon the coarseness and crystal structure of its underlying substrate surface. There is also a possibility that the quality of the film (the presence or absence of the defect) will differ depending upon the shape of the surface. There are sometimes the cases that, by the native oxide film on the substrate surface immediately prior to the growth or a damage, etc., produced at the time of forming a gate electrode, for example, the thickness of the silicon layer formed as a film on the source/drain region and its film quality differ from element to element.
If the thickness of the selectively grown silicon layer is not uniform, it becomes very difficult to form a pn junction area at a predetermined position. Since an impurity with which the source/drain region is to be formed is introduced from the selectively formed silicon layer surface, this junction is formed at a predetermined position from that surface. If, on the other hand, the film thickness is not uniform, then a relative position of an additively formed silicon surface relative to the surface of the silicon substrate becomes indefinite and hence the position of the junction surface to be formed also becomes indefinite.
For this reason, prior to the selective growth of the silicon, it is necessary to remove the damaged layer.
Then, as shown in
FIG. 5C
, the damaged layer
16
is removed. In order to remove the damaged layer
16
, use is made of a wet treatment using chemicals, such as a hydrofluoric acid
itric acid-mixed solution or a CDE method using lower kinetic energy radicals generated in a CF
4
or Cl
2
gas plasma and, by doing this, the Si substrate is isotropically etched to remove any damage involved.
Then, as shown in
FIG. 5D
, silicon
18
,
19
is selectively grown. It is to be noted that, on the silicon substrate, an epitaxial growth is produced to provide a single crystalline silicon
18
. And an n-type impurity ion is implanted and annealing is performed to form source/drain regions
20
.
And, as shown in
FIG. 5E
, after the deposition of Co, annealing is performed to form Co silicide
22
and unreacted Co is eliminated to form a MOS transistor having an elevated source/drain structure.
Although the removal of the damaged layer is carried out by etching the silicon substrate, the etching amount of the silicon substrate greatly depends upon a damaged amount of the damaged layer and exposed amount of the silicon substrate surface and, since an unstable process is involved, it is difficult to control the etching amount. If any reliable product tries to be produced, then it is necessary to etch the silicon substrate considerably excessively.
On the other hand, there has been a tendency that, due to the miniaturization of the semiconductor device, the diffusion layer formed in the silicon substrate surface portion becomes shallower in depth. If, therefore, the damaged layer is removed by the above-mentioned procedure, it follows that not only the damaged layer but also the non-defective silicon substrate is deeply eliminated. As a result, the diffused layer becomes shallower in depth and an electric defect occurs, thus presenting a problem.
BRIEF SUMMARY OF THE INVENTION
It is accordingly the object of the present invention to provide a method for manufacturing a semiconductor device which eliminates a damaged layer under better control and suppresses the generation of an electric defect.
In order to achieve the above-mentioned object of the present invention, the present invention has been achieved as will be set out below.
(a) A manufacturing method of a semiconductor device according to the present invention comprises the steps of forming a damaged layer on a surface of a silicon substrate by subjecting the silicon substrate to a plasma treatment, forming a silicon oxide layer by exposing the surface of the damaged layer to an oxygen plasma to oxidize a surface of the silicon substrate includ
Hayashi Hisataka
Ohiwa Tokuhisa
Okumura Katsuya
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Le Vu A.
Owens Beth E.
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