Method to crown capacitor for high density DRAM

Details Method to crown capacitor for high density DRAM Method to crown capacitor for high density DRAM

1999-01-25

2001-04-10

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S671000, C438S717000, C438S950000

Reexamination Certificate

active

06214659

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a capacitor. More particularly, the present invention relates to a method for fabricating a crown capacitor used in DRAM.
2. Description of the Related Art
In conventional DRAM having a storage capacity less than 1 MB, it is a customary practice to use a two-dimensional capacitor called a planar-type capacitor as the data storage capacitor. One drawback in the planar-type capacitor, however, is that it requires quite a large chip area to implement. Therefore, the planar-type capacitor is not suitable for high-integration DRAM. In DRAM having a storage capacity higher than 4 MB, a three-dimensional capacitor such as a stacked-type capacitor is used as the data storage capacitor. A crown capacitor is a kind of stacked-type capacitor.
FIGS. 1A through 1C
are schematic, cross-sectional diagrams used to depict the steps in conventional method for fabricating a crown capacitor
Referring to
FIG. 1A
, a substrate
20
having a MOS structure is provided, wherein the MOS structure includes a drain region
24
. An inter-layer dielectric layer
26
is formed on the substrate
20
. A contact hole
28
is formed in the inter-dielectric layer
26
to expose the drain region
24
. A conductive layer
30
is formed on the inter-layer dielectric layer
26
and fills the contact hole
28
. The thickness of the conductive layer
30
on the inter-layer dielectric layer
26
is about 6000 Å.
Referring to
FIG. 1B
, an opening
32
is formed in the conductive layer
30
and corresponds to the contact hole
28
. The step of forming the opening
32
includes performing an anisotropic etching process to remove a portion of the conductive layer
30
by controlling the duration of etching. The depth of etching is about 4000 to 5000 Å.
Referring to
FIG. 1C
, an anisotropic etching process is performed to remove a portion of the conductive layer
30
by using the inter-layer dielectric layer
26
as a stop layer. Therefore, a bottom electrode
34
is made from the remaining conductive layer
30
. A dielectric layer
36
is formed on the bottom electrode
34
and an upper electrode
38
is formed on the dielectric layer
36
.
In conventional process for fabricating DRAM whose channel length is below 0.35 &mgr;m, two masks are used to form the bottom electrode of the crown capacitor. As the integration of DRAM is increased, the critical dimension of the crown capacitor is reduced. It is hard to meet the demands of the critical dimension of the crown capacitor by using conventional process, because the tolerance of the registration between the two masks is reduced.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for fabricating a crown capacitor useing only one mask to meet the demand of the critical dimension of the crown capacitor.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating a crown capacitor. The method for fabricating this crown capacitor includes the following steps. A substrate having a MOS structure is provided. The MOS structure includes a drain region. An inter-layer dielectric layer is formed on the substrate. A contact hole is formed in the inter-layer dielectric layer to expose the drain region. A first conductive layer is formed on the inter-layer dielectric layer and fills the contact hole. A first, deep UV photoresist layer and a hard mask layer are formed in sequence on the first conductive layer. A second, deep UV photoresist layer is formed on a portion of the hard mask layer and corresponding to the contact hole. A portion of the hard mask layer is removed. The second deep UV photoresist layer and a portion of the first deep UV photoresist layer are removed. A second, conductive layer is formed on the sidewall of the first, deep UV photoresist layer by performing a silylation process. A portion of the first conductive layer exposed by the first, deep UV photoresist layer and the second conductive layer is removed by performing an anisotropic etching process, and a portion of the top of the second conductive layer is removed in the same step. A bottom electrode of the crown capacitor is made from the remaining first conductive layer and the remaining second conductive layer. Then, the hard mask layer and the remaining first, deep UV photoresist layer are removed in sequence. A dielectric layer is formed on the bottom electrode. Finally, an upper electrode is formed on the dielectric layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides another method for fabricating a crown capacitor. The method for fabricating this crown capacitor includes the following steps. A substrate having a MOS structure is provided, wherein the MOS structure includes a drain region. An inter-layer dielectric layer is formed on the substrate. A contact hole is formed in the inter-layer dielectric layer to expose the drain region. A first conductive layer is formed on the inter-layer dielectric layer and fills the contact hole. A deep UV photoresist layer is formed on the first conductive layer. The deep UV photoresist layer is patterned, thus the remaining deep UV photoresist layer having cylindrical structure corresponds to the contact hole. A second conductive layer is formed on the top and the sidewall of the remaining deep UV photoresist layer by performing a silylation process. A portion of the first conductive layer exposed by the second conductive layer and the deep UV photoresist layer is removed, and a portion of the second conductive layer is removed in the same step. A bottom electrode of the crown capacitor is made from the remaining first conductive layer and the remaining second conductive layer. Then, the remaining deep UV photoresist layer is removed. A dielectric layer is formed on the bottom electrode. An upper electrode is formed on the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5127987 (1992-07-01), Okudaira et al.
patent: 5407529 (1995-04-01), Homma
patent: 5871886 (1999-02-01), Yu et al.
patent: 6124162 (2000-09-01), Lin
Wolf et al., “Lithography I: Optical Resist Materials and Process Technology”, Silicon Processing for the VLSI Era, vol. 1—Process Technology (pp. 427-428), 1986.

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