Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-15
2001-09-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06291288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of fabricating a dielectric structure for a storage capacitor in dynamic random-access memory (DRAM).
2. Description of Related Art
With the advent of advanced and state-of-the-art semiconductor fabrication technologies, IC devices are now being downsized to the submicron or even deep submicron levels of integration to provide extremely high packing densities of transistor elements therein. In the case of DRAM, however, the downsizing would also reduce the capacitance of its storage capacitor, resulting in a degraded data retaining capability.
The storage capacitor in each DRAM cell is composed of a pair of oppositely arranged electrodes and a dielectric structure sandwiched therebetween. Fundamentally, the data retaining capability of the DRAM increases with the capacitance of its storage capacitor; and the capacitance of the storage capacitor is proportional to the dielectric constant of the dielectric structure and inversely proportional to the thickness of the dielectric structure. The dielectric structure is typically formed from silicon oxide or silicon nitride. Silicon oxide has a dielectric constant of about 3.8, and silicon nitride has a dielectric constant of about 7. Therefore, silicon nitride is more preferable than silicon oxide as the dielectric material used to form DRAM's storage capacitor.
A silicon nitride based dielectric layer is conventionally formed through a low-pressure chemical-vapor disposition (LPCVD) process, with SiH
2
Cl
2
or SiH
4
serving as the reactant to be reacted with NH
3
for the forming of silicon nitride. One drawback to the use of LPCVD process to form silicon nitride based dielectric layer, however, is that when the thickness is downsized to below 200 Å, it would cause the resultant silicon nitride layer to be formed with an undesired rugged surface with many punctures, which would make the resultant storage capacitor to suffer from leakage current, and thus unreliable to use. This structural defect can be eliminated by increasing the thickness of the silicon nitride layer. However, this would make the resultant storage capacitor low in capacitance.
One solution to the foregoing problem is to use an ONO dielectric structure, which is a stacked structure consisting of a first oxide layer (O), a silicon nitride layer (N) over the first oxide layer, and a second oxide layer (O) over the silicon nitride layer. Typically, the first oxide layer is a primitive oxide layer; while the second oxide layer is formed through a wet-oxidation process, by which the wafer is placed in an oven with water serving as the oxidant to undergo a thermal oxidation process at a temperature of 800° C. for a continuous period of about 30 minutes. This process can help mend the above-mentioned structural defect in the resultant silicon nitride layer to prevent the leak-age problem.
One drawback to the foregoing method, however, is that the effective dielectric constant of the overall dielectric structure would be decreased due to the use of two oxide layers and the increased thickness from the wet-oxidation process. The capacitance of the resultant storage capacitor is therefore still unsatisfactorily low.
There exists, therefore, a need for a new semiconductor fabrication method that can allow the dielectric structure between the electrodes of a storage capacitor in DRAM to be as thin as possible while nevertheless allowing the resultant dielectric structure to be substantially free from the above-mentioned structural defect.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a method for fabricating a dielectric structure for a storage capacitor in DRAM, which allows the resultant dielectric structure to be thinner as compared to the prior art to the level of from 30 Å to 50 Å so as to provide a high dielectric constant to allow a high capacitance for the DRAM's storage capacitor.
It is another objective of this invention to provide a method for fabricating a di-electric structure for a storage capacitor in DRAM, which allows the resultant dielectric structure to be substantially free from such a structural defect as a rugged surface with punctures so as to allow the resultant DRAM to be free from leakage problem.
In accordance with the foregoing and other objectives of this invention, an improved semiconductor fabrication method is provided for fabricating a dielectric structure for a storage capacitor in DRAM.
The method of the invention is used to fabricate a dielectric structure between a first electrode and a second electrode for a storage capacitor in DRAM. The first electrode is formed with a primitive oxide layer thereon. The method of the invention comprises the steps of: (1) removing the primitive oxide layer; (2) performing a first nitridation process to form a dielectric layer over the first electrode; (3) forming a layer of silicon nitride over the dielectric layer; and (4) performing a second nitridation process on the silicon nitride layer, with the resultant silicon nitride layer and the dielectric layer in combination constituting an ON structure serving as the intended dielectric structure. Alternatively, an oxide layer can be further formed over the silicon nitride layer, with the dielectric layer, the silicon nitride layer, and the oxide layer in combination constituting an ONO structure serving as the intended dielectric structure.
The second nitridation process can be carried out either through a rapid thermal treatment process with the use of a reactant selected from nitrogen, ammonia, and a mixture of nitrogen and ammonia under a temperature of from 800° C. to 1,000° C. for a continuous period of from 30 to 60 seconds; or through a nitrogen plasma treatment process under a temperature of from 400° C. to 600° C.
The method of the invention has the following advantages over the prior art. First, the invention can help improve the structural quality of the silicon nitride layer, allowing the resultant silicon nitride layer to be formed substantially without a rugged surface with punctures. This not only can help solve the leakage problem of the prior art, but also can help further downsize the thickness of the silicon nitride layer, resulting in a larger capacitance for the DRAM data storage capacitor. Second, the step of forming a silicon oxide layer can be eliminated. Moreover, the thinning of the primitive oxide layer can also help downsize the overall thickness of the dielectric structure so that the capacitance of the resultant storage capacitor can be increased. Third, the use of rapid thermal treatment or nitrogen plasma treatment under low temperature conditions allows a low thermal budget to the fabrication of the storage capacitor and also helps to improve the short-channel effect between the source and drain of each transistor element in the DRAM that would otherwise occur due to multiple thermal treatment steps to the impurity-doped regions. Fourth, the invention allows the overall fabrication process to be easier to carry out due to the fact that the step of performing the first nitridation process to the step of forming the second electrode can be all carried out on the same platform without having to redispose the wafer from the vacuum chamber.
REFERENCES:
patent: 4996081 (1991-02-01), Ellul et al.
patent: 5913149 (1999-06-01), Thakur et al.
patent: 6063713 (2000-05-01), Doan
patent: 6077754 (2000-06-01), Srinivasan et al.
Huang Kuo-Tai
Yew Tri-Rung
Hoang Quoc
Nelms David
United Microelectronics Corp.
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