Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-10-10
2001-01-30
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S696000, C438S634000
Reexamination Certificate
active
06180517
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuit processing, and more specifically to an improved method of forming submicron contacts and vias.
BACKGROUND OF THE INVENTION
As is well known in the field of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions. These geometries and sizes are often dependent upon the current photolithographic equipment and materials available in the industry. The equipment and masks used in photolithography project an image of patterns onto a wafer surface. One of the important characteristics in VLSI fabrication is the resolution or the optical system's ability to distinguish closely spaced objects. The resolution of the system is one of the main limitations of achieving minimum device sizes required. In establishing the horizontal dimensions of the various devices and circuits, a pattern must be created which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer. As line widths shrink smaller and smaller in submicron photolithography, the process to print lines and contact holes in photoresist becomes increasingly more difficult.
In semiconductor processing, semiconductive and conductive regions or layers are formed and subsequently interconnected to create components and circuits. The lithographic process uses patterns to define these regions. One of the critical steps is the interconnection of two conducting layers on different levels that are separated by an insulating layer, especially when one of the conductive layers is the top metal layer. Presently, an underlying conductor layer is covered with an interlevel oxide layer and then the contact or via is formed therein to expose the surface of the underlying conductor layer at a selected region. A top conducting layer is then patterned and interconnected through the contact or via with the underlying conducting material. This underlying conducting material can comprise either a conductive layer of polysilicon or metal or even an active area on or in the silicon surface itself.
Conventional technology shrink such as forming contacts and vias has been done primarily through improvements in photolithography capability. The dependency on photolithography to achieve adequate projection of images of patterns onto the wafer surfaces is limited by the photolithography equipment's capability, especially as feature sizes continue to decrease. To go beyond technology at any given point in time and achieve the required technology shrink may well require new photolithography equipment. However, technology continues to push the limit on current equipment. Thus, it would be desirable to achieve device sizes below the current photolithography capability.
Accordingly, it is an object of the present invention to provide a method of forming submicron contacts and vias.
It is a further object of the present invention to provide such a method of forming contacts and vias having feature sizes below that which is capable of being produced with current photolithography technology and without sacrificing device performance.
It is yet another object of the present invention to provide such a method of forming contacts and vias having contact dimensions smaller than the contact dimensions which can be printed with modern photolithography equipment.
It is still further an object of the present invention to provide such a method which utilizes conventional process techniques.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification, together with its drawings.
SUMMARY OF THE INVENTION
The invention may be incorporated into a method of forming small geometry vias and contacts of a semiconductor device structure, and the semiconductor device structure formed thereby, by forming sidewall spacers along the sides of the via and contact openings. According to a first embodiment of the invention, an opening is made partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sides of the opening. The top of the sidewall spacers are below the top of the insulating layer by a distance approximately equal to the thickness of the remaining insulating layer in the opening. The insulating layer is then anisotropically etched to expose the conductive region. An upper surface of the insulating layer may also be removed in the etch step by a substantially equivalent thickness causing the upper layer to be substantially planar with the top of the sidewall spacers. According to an alternate embodiment, the opening in the insulating layer exposes the underlying conductive region. A conformal polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening. The oxidized polysilicon is anisotropically etched to form oxidized polysilicon sidewall spacers. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and the conductive region. The opening in the insulating layer exposes the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer in the opening. The etch stop layer and the sidewall spacer film have similar etch rates for a given etchant and are etched to expose the underlying conductive region. This etch step forms a contiguous sidewall spacer and etch stop layer along the sidewalls of the opening and under the insulating layer. The present invention provides for via and contact geometries which are smaller than geometries achievable with modern photolithographic equipment and photoresists.
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Liou Fu-Tai
Zamanian Mehdi
Everhart Caridad
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Venglarik Dan
LandOfFree
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